diff options
author | drochner <drochner@pkgsrc.org> | 2003-07-14 09:51:48 +0000 |
---|---|---|
committer | drochner <drochner@pkgsrc.org> | 2003-07-14 09:51:48 +0000 |
commit | b5144ee56e949592461f724cc44e1ef2ba6506ab (patch) | |
tree | 1740492d6847ecb2b50f60b9c7931573e0a85863 | |
parent | 1f6effdcafe78cf7df6584d483c90018e98e77f3 (diff) | |
download | pkgsrc-b5144ee56e949592461f724cc44e1ef2ba6506ab.tar.gz |
update to snapshot "20030705".
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added
Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.
-rw-r--r-- | cad/verilog-current/Makefile | 8 | ||||
-rw-r--r-- | cad/verilog-current/PLIST | 4 | ||||
-rw-r--r-- | cad/verilog-current/distinfo | 8 | ||||
-rw-r--r-- | cad/verilog-current/patches/patch-ad | 13 |
4 files changed, 18 insertions, 15 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index 626c3ac3726..77b4db69518 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.32 2003/02/04 00:46:07 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.33 2003/07/14 09:51:48 drochner Exp $ # DISTNAME= verilog-${SNAPDATE} @@ -17,7 +17,8 @@ BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf CONFLICTS+= verilog-[0-9]* -SNAPDATE= 20030202 +SNAPDATE= 20030705 +USE_BUILDLINK2= yes GNU_CONFIGURE= yes USE_GMAKE= yes # @@ -29,4 +30,7 @@ YACC= ${LOCALBASE}/bin/bison TEST_DIRS= ${WRKSRC} TEST_TARGET= check +.include "../../devel/zlib/buildlink2.mk" +.include "../../archivers/bzip2/buildlink2.mk" +.include "../../devel/readline/buildlink2.mk" .include "../../mk/bsd.pkg.mk" diff --git a/cad/verilog-current/PLIST b/cad/verilog-current/PLIST index d357e2cdfa5..135223d5d12 100644 --- a/cad/verilog-current/PLIST +++ b/cad/verilog-current/PLIST @@ -1,13 +1,15 @@ -@comment $NetBSD: PLIST,v 1.4 2002/08/24 04:36:44 dmcmahill Exp $ +@comment $NetBSD: PLIST,v 1.5 2003/07/14 09:51:48 drochner Exp $ bin/iverilog bin/iverilog-vpi bin/vvp +include/_pli_types.h include/acc_user.h include/ivl_target.h include/veriuser.h include/vpi_user.h lib/libveriuser.a lib/libvpi.a +lib/ivl/cadpli.vpl lib/ivl/fpga.tgt lib/ivl/ivl lib/ivl/iverilog.conf diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index 9b3baf280c7..5273729016b 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,5 +1,5 @@ -$NetBSD: distinfo,v 1.16 2003/02/04 00:46:07 dmcmahill Exp $ +$NetBSD: distinfo,v 1.17 2003/07/14 09:51:48 drochner Exp $ -SHA1 (verilog-20030202.tar.gz) = 9bf846546bde334d251c0c5c7f191b3d76fa159c -Size (verilog-20030202.tar.gz) = 829887 bytes -SHA1 (patch-ad) = dbf85e203f91d0df3a8aed12494a6de83b3f6c40 +SHA1 (verilog-20030705.tar.gz) = 1f6d0284b8efa63441e8b2650d11df434a48f374 +Size (verilog-20030705.tar.gz) = 910118 bytes +SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a diff --git a/cad/verilog-current/patches/patch-ad b/cad/verilog-current/patches/patch-ad index db51381738a..994781c9ebb 100644 --- a/cad/verilog-current/patches/patch-ad +++ b/cad/verilog-current/patches/patch-ad @@ -1,11 +1,8 @@ -$NetBSD: patch-ad,v 1.11 2003/02/04 00:46:08 dmcmahill Exp $ +$NetBSD: patch-ad,v 1.12 2003/07/14 09:51:49 drochner Exp $ -work around a c++ -O2 bug which is present on at least sparc -and pmax using egcs-1.1.1 - ---- Makefile.in.orig Sun Jan 26 16:15:58 2003 -+++ Makefile.in -@@ -174,7 +174,17 @@ +--- Makefile.in.orig 2003-06-25 03:48:39.000000000 +0200 ++++ Makefile.in 2003-07-12 19:11:41.000000000 +0200 +@@ -170,7 +170,17 @@ lexor.o: lexor.cc parse.h @@ -21,5 +18,5 @@ and pmax using egcs-1.1.1 + $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o + mv $*.d dep/$*.d - parse.h parse.cc: $(srcdir)/parse.y + parse.cc: $(srcdir)/parse.y $(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y |