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author | drochner <drochner> | 2009-04-01 17:26:06 +0000 |
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committer | drochner <drochner> | 2009-04-01 17:26:06 +0000 |
commit | 99a1e020823ba2a72cfe6ebd8ede63fece43cb03 (patch) | |
tree | 52bd4e48a08bbd0392abb7cbb574ebb35e553e4a | |
parent | 7deb5bc1c673f7d672a221f8bc08c1c94e0ee70d (diff) | |
download | pkgsrc-99a1e020823ba2a72cfe6ebd8ede63fece43cb03.tar.gz |
this needs verilog-current to build
-rw-r--r-- | cad/MyHDL-iverilog/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile index 0bc256d3f75..1b89b0cd81f 100644 --- a/cad/MyHDL-iverilog/Makefile +++ b/cad/MyHDL-iverilog/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.4 2008/03/03 01:50:26 jlam Exp $ +# $NetBSD: Makefile,v 1.5 2009/04/01 17:26:06 drochner Exp $ # DISTNAME= myhdl-0.5.1 @@ -19,5 +19,5 @@ do-install: ${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \ ${DESTDIR}${PREFIX}/lib/ivl -.include "../../cad/verilog/buildlink3.mk" +.include "../../cad/verilog-current/buildlink3.mk" .include "../../mk/bsd.pkg.mk" |