import covered-0.2.1

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?".  When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.

1 files changed, 5 insertions, 0 deletions

diff --git a/cad/covered/distinfo b/cad/covered/distinfo
new file mode 100644
index 00000000000..17188d387be
--- /dev/null
+++ b/cad/covered/distinfo
@@ -0,0 +1,5 @@
+$NetBSD: distinfo,v 1.1.1.1 2003/08/24 18:38:06 dmcmahill Exp $
+
+SHA1 (covered-0.2.1.tar.gz) = 5cd7bc57d7fbbb647472dd23040adca6e72a3d0e
+Size (covered-0.2.1.tar.gz) = 525420 bytes
+SHA1 (patch-aa) = 0ffd830e411c00d5fa1776f14e949362b2d2980f