import covered-0.2.1

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?".  When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.

5 files changed, 75 insertions, 0 deletions

diff --git a/cad/covered/DESCR b/cad/covered/DESCR
new file mode 100644
index 00000000000..3a3de8062a5
--- /dev/null
+++ b/cad/covered/DESCR
@@ -0,0 +1,17 @@
+Covered is a Verilog code coverage analysis tool that can be useful
+for determining how well a diagnostic test suite is covering the
+design under test. Typically in the design verification work flow, a
+design verification engineer will develop a self-checking test suite
+to verify design elements/functions specified by a design's
+specification document. When the test suite contains all of the tests
+required by the design specification, the test writer may be asking
+him/herself, "How much logic in the design is actually being
+exercised?", "Does my test suite cover all of the logic under test?",
+and "Am I done writing tests for the logic?".  When the design
+verification gets to this point, it is often useful to get some
+metrics for determining logic coverage. This is where a code coverage
+utility, such as Covered, is very useful.
+
+Please note that this package is for a stable release version.
+There is a seperate package (covered-current) which is made of
+development snapshots.
diff --git a/cad/covered/Makefile b/cad/covered/Makefile
new file mode 100644
index 00000000000..8011c1920e0
--- /dev/null
+++ b/cad/covered/Makefile
@@ -0,0 +1,28 @@
+# $NetBSD: Makefile,v 1.1.1.1 2003/08/24 18:38:06 dmcmahill Exp $
+#
+
+DISTNAME=	covered-0.2.1
+CATEGORIES=	cad
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=covered/}
+
+MAINTAINER=	dmcmahill@NetBSD.org
+HOMEPAGE=	http://covered.sourceforge.net/
+COMMENT=	Verilog code coverage analyzer (stable release version)
+
+BUILD_DEPENDS+=	bison-[0-9]*:../../devel/bison
+BUILD_DEPENDS+=	gperf-2.7.2:../../devel/gperf
+DEPENDS+=	verilog{,-current}-[0-9]*:../../cad/verilog
+
+CONFLICTS+=	covered-current-[0-9]*
+
+USE_PERL5=	YES
+REPLACE_PERL=	${WRKSRC}/diags/verilog/check_test
+GNU_CONFIGURE=	YES
+USE_GMAKE=	YES
+TEST_DIRS=	${WRKSRC}/diags/regress
+TEST_TARGET=	#defined
+
+post-patch:
+	${CHMOD} 755 ${WRKSRC}/missing
+
+.include "../../mk/bsd.pkg.mk"
diff --git a/cad/covered/PLIST b/cad/covered/PLIST
new file mode 100644
index 00000000000..0d7fdaee7cd
--- /dev/null
+++ b/cad/covered/PLIST
@@ -0,0 +1,3 @@
+@comment $NetBSD: PLIST,v 1.1.1.1 2003/08/24 18:38:06 dmcmahill Exp $
+bin/covered
+man/man1/covered.1
diff --git a/cad/covered/distinfo b/cad/covered/distinfo
new file mode 100644
index 00000000000..17188d387be
--- /dev/null
+++ b/cad/covered/distinfo
@@ -0,0 +1,5 @@
+$NetBSD: distinfo,v 1.1.1.1 2003/08/24 18:38:06 dmcmahill Exp $
+
+SHA1 (covered-0.2.1.tar.gz) = 5cd7bc57d7fbbb647472dd23040adca6e72a3d0e
+Size (covered-0.2.1.tar.gz) = 525420 bytes
+SHA1 (patch-aa) = 0ffd830e411c00d5fa1776f14e949362b2d2980f
diff --git a/cad/covered/patches/patch-aa b/cad/covered/patches/patch-aa
new file mode 100644
index 00000000000..779fce89ac2
--- /dev/null
+++ b/cad/covered/patches/patch-aa
@@ -0,0 +1,22 @@
+$NetBSD: patch-aa,v 1.1.1.1 2003/08/24 18:38:06 dmcmahill Exp $
+
+--- doc/Makefile.orig	Sun Aug 17 03:13:41 2003
++++ doc/Makefile
+@@ -1,13 +1,13 @@
+ all:
+ 	- doxygen covered.dox
+-	- cd ./user; make all
++	- cd ./user; ${MAKE} all
+ 
+ install:
+-	- cd ./user; make install
++	- cd ./user; ${MAKE} install
+ 
+ uninstall:
+-	- cd ./user; make uninstall
++	- cd ./user; ${MAKE} uninstall
+ 
+ clean:
+ 	rm -rf ./devel/html ./devel/latex
+-	- cd ./user; make clean
++	- cd ./user; ${MAKE} clean