diff options
author | jmmv <jmmv@pkgsrc.org> | 2003-05-06 17:40:18 +0000 |
---|---|---|
committer | jmmv <jmmv@pkgsrc.org> | 2003-05-06 17:40:18 +0000 |
commit | f1446ddf2bf8118f432b3ac74c88db3d832669a8 (patch) | |
tree | 37ae7d212f46ef8018a7bd8c13edba7da1a47ed9 /cad/electric | |
parent | 37170ce899bdf394cca1d0769b2215d84b15a7ee (diff) | |
download | pkgsrc-f1446ddf2bf8118f432b3ac74c88db3d832669a8.tar.gz |
Drop trailing whitespace. Ok'ed by wiz.
Diffstat (limited to 'cad/electric')
-rw-r--r-- | cad/electric/DESCR | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/cad/electric/DESCR b/cad/electric/DESCR index d9c70d052b2..22823ed258c 100644 --- a/cad/electric/DESCR +++ b/cad/electric/DESCR @@ -1,20 +1,20 @@ Electric is a sophisticated electrical CAD system that can handle -many forms of circuit design, including: +many forms of circuit design, including: Custom IC layout (ASICs), Schematic drawing, Hardware description - language specifications, Electro-mechanical hybrid layout + language specifications, Electro-mechanical hybrid layout -Electric has these CAD operations: - Design rule checking (3 options), Electrical rule checking, - Simulation and simulation interface (12 options), Generation (3 options), +Electric has these CAD operations: + Design rule checking (3 options), Electrical rule checking, + Simulation and simulation interface (12 options), Generation (3 options), Compaction, Compensation, Routing (4 options), VHDL compilation, - Silicon compilation, Network consistency checking (LVS), - Logical Effort analysis, Project Management + Silicon compilation, Network consistency checking (LVS), + Logical Effort analysis, Project Management -Electric handles these types of design: +Electric handles these types of design: MOS (6 CMOS variations, 1 nMOS variation), Bipolar and BiCMOS, - Schematics and printed circuits, Digital filters, Temporal logic, Artwork + Schematics and printed circuits, Digital filters, Temporal logic, Artwork -Electric handles these file formats: +Electric handles these file formats: CIF I/O, GDS I/O, EDIF I/O, DXF I/O, SDF Input, - SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output, - PostScript, HPGL, and QuickDraw output + SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output, + PostScript, HPGL, and QuickDraw output |