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| author | drochner <drochner@pkgsrc.org> | 2006-02-10 16:06:46 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2006-02-10 16:06:46 +0000 |
| commit | 4ca0722c59c3c3cc367a0360212dba8a64731f44 (patch) | |
| tree | 1d870de43aaadffb33488a8b72aaf165b69119cf /cad/py-MyHDL/Makefile | |
| parent | 123d8ca9fefd300f362fb9eb9a077cd14f3d17ae (diff) | |
| download | pkgsrc-4ca0722c59c3c3cc367a0360212dba8a64731f44.tar.gz | |
update to 0.5
major changes:
-supports Python decorator syntax for generators (needs 2.4)
-intbv() doesn't have a default anymore
-many improvements to Verilog conversion
Diffstat (limited to 'cad/py-MyHDL/Makefile')
| -rw-r--r-- | cad/py-MyHDL/Makefile | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile index 53590f6a464..56398018e7d 100644 --- a/cad/py-MyHDL/Makefile +++ b/cad/py-MyHDL/Makefile @@ -1,9 +1,8 @@ -# $NetBSD: Makefile,v 1.10 2006/02/05 23:08:22 joerg Exp $ +# $NetBSD: Makefile,v 1.11 2006/02/10 16:06:46 drochner Exp $ # -DISTNAME= myhdl-0.4.1 -PKGNAME= ${PYPKGPREFIX}-MyHDL-0.4.1 -PKGREVISION= 1 +DISTNAME= myhdl-0.5 +PKGNAME= ${PYPKGPREFIX}-MyHDL-0.5 CATEGORIES= cad python MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/} @@ -12,7 +11,10 @@ HOMEPAGE= http://jandecaluwe.com/Tools/MyHDL/Overview.html COMMENT= Hardware description in Python PYDISTUTILSPKG= yes -PYTHON_VERSIONS_ACCEPTED= 23 24 +PYTHON_VERSIONS_ACCEPTED= 24 + +do-test: + cd ${WRKSRC}/myhdl/test && ${PYTHONBIN} test_all.py .include "../../lang/python/extension.mk" .include "../../mk/bsd.pkg.mk" |