diff options
| author | drochner <drochner@pkgsrc.org> | 2005-01-05 15:20:10 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2005-01-05 15:20:10 +0000 |
| commit | 154f18aa7daf3f2aef2697c6c0acd7794862e32e (patch) | |
| tree | fbf8a4e75b09174b530c71d67084f5fb6acf013c /cad/py-MyHDL/PLIST | |
| parent | 28db861b64a3b63cea68e623be1134767152fe8e (diff) | |
| download | pkgsrc-154f18aa7daf3f2aef2697c6c0acd7794862e32e.tar.gz | |
update to 0.4.1
changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes
Diffstat (limited to 'cad/py-MyHDL/PLIST')
| -rw-r--r-- | cad/py-MyHDL/PLIST | 99 |
1 files changed, 65 insertions, 34 deletions
diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST index 70a5d83aea6..89d54ecf890 100644 --- a/cad/py-MyHDL/PLIST +++ b/cad/py-MyHDL/PLIST @@ -1,41 +1,72 @@ -@comment $NetBSD: PLIST,v 1.2 2003/09/14 16:43:46 recht Exp $ -${PYSITELIB}/myhdl/Cosimulation.py -${PYSITELIB}/myhdl/Cosimulation.pyc -${PYSITELIB}/myhdl/Cosimulation.pyo -${PYSITELIB}/myhdl/Signal.py -${PYSITELIB}/myhdl/Signal.pyc -${PYSITELIB}/myhdl/Signal.pyo -${PYSITELIB}/myhdl/Simulation.py -${PYSITELIB}/myhdl/Simulation.pyc -${PYSITELIB}/myhdl/Simulation.pyo +@comment $NetBSD: PLIST,v 1.3 2005/01/05 15:20:10 drochner Exp $ +${PYSITELIB}/myhdl/_Cosimulation.py +${PYSITELIB}/myhdl/_Cosimulation.pyc +${PYSITELIB}/myhdl/_Cosimulation.pyo +${PYSITELIB}/myhdl/_Signal.py +${PYSITELIB}/myhdl/_Signal.pyc +${PYSITELIB}/myhdl/_Signal.pyo +${PYSITELIB}/myhdl/_Simulation.py +${PYSITELIB}/myhdl/_Simulation.pyc +${PYSITELIB}/myhdl/_Simulation.pyo +${PYSITELIB}/myhdl/_Waiter.py +${PYSITELIB}/myhdl/_Waiter.pyc +${PYSITELIB}/myhdl/_Waiter.pyo ${PYSITELIB}/myhdl/__init__.py ${PYSITELIB}/myhdl/__init__.pyc ${PYSITELIB}/myhdl/__init__.pyo +${PYSITELIB}/myhdl/_always_comb.py +${PYSITELIB}/myhdl/_always_comb.pyc +${PYSITELIB}/myhdl/_always_comb.pyo +${PYSITELIB}/myhdl/_bin.py +${PYSITELIB}/myhdl/_bin.pyc +${PYSITELIB}/myhdl/_bin.pyo +${PYSITELIB}/myhdl/_cell_deref.py +${PYSITELIB}/myhdl/_cell_deref.pyc +${PYSITELIB}/myhdl/_cell_deref.pyo +${PYSITELIB}/myhdl/_concat.py +${PYSITELIB}/myhdl/_concat.pyc +${PYSITELIB}/myhdl/_concat.pyo +${PYSITELIB}/myhdl/_delay.py +${PYSITELIB}/myhdl/_delay.pyc +${PYSITELIB}/myhdl/_delay.pyo +${PYSITELIB}/myhdl/_enum.py +${PYSITELIB}/myhdl/_enum.pyc +${PYSITELIB}/myhdl/_enum.pyo +${PYSITELIB}/myhdl/_extractHierarchy.py +${PYSITELIB}/myhdl/_extractHierarchy.pyc +${PYSITELIB}/myhdl/_extractHierarchy.pyo +${PYSITELIB}/myhdl/_intbv.py +${PYSITELIB}/myhdl/_intbv.pyc +${PYSITELIB}/myhdl/_intbv.pyo +${PYSITELIB}/myhdl/_isGenSeq.py +${PYSITELIB}/myhdl/_isGenSeq.pyc +${PYSITELIB}/myhdl/_isGenSeq.pyo +${PYSITELIB}/myhdl/_join.py +${PYSITELIB}/myhdl/_join.pyc +${PYSITELIB}/myhdl/_join.pyo +${PYSITELIB}/myhdl/_misc.py +${PYSITELIB}/myhdl/_misc.pyc +${PYSITELIB}/myhdl/_misc.pyo ${PYSITELIB}/myhdl/_simulator.py ${PYSITELIB}/myhdl/_simulator.pyc ${PYSITELIB}/myhdl/_simulator.pyo -${PYSITELIB}/myhdl/delay.py -${PYSITELIB}/myhdl/delay.pyc -${PYSITELIB}/myhdl/delay.pyo -${PYSITELIB}/myhdl/intbv.py -${PYSITELIB}/myhdl/intbv.pyc -${PYSITELIB}/myhdl/intbv.pyo -${PYSITELIB}/myhdl/test_Cosimulation.py -${PYSITELIB}/myhdl/test_Cosimulation.pyc -${PYSITELIB}/myhdl/test_Cosimulation.pyo -${PYSITELIB}/myhdl/test_Signal.py -${PYSITELIB}/myhdl/test_Signal.pyc -${PYSITELIB}/myhdl/test_Signal.pyo -${PYSITELIB}/myhdl/test_Simulation.py -${PYSITELIB}/myhdl/test_Simulation.pyc -${PYSITELIB}/myhdl/test_Simulation.pyo -${PYSITELIB}/myhdl/test_all.py -${PYSITELIB}/myhdl/test_all.pyc -${PYSITELIB}/myhdl/test_all.pyo -${PYSITELIB}/myhdl/test_intbv.py -${PYSITELIB}/myhdl/test_intbv.pyc -${PYSITELIB}/myhdl/test_intbv.pyo -${PYSITELIB}/myhdl/util.py -${PYSITELIB}/myhdl/util.pyc -${PYSITELIB}/myhdl/util.pyo +${PYSITELIB}/myhdl/_toVerilog/__init__.py +${PYSITELIB}/myhdl/_toVerilog/__init__.pyc +${PYSITELIB}/myhdl/_toVerilog/__init__.pyo +${PYSITELIB}/myhdl/_toVerilog/_analyze.py +${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc +${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo +${PYSITELIB}/myhdl/_toVerilog/_convert.py +${PYSITELIB}/myhdl/_toVerilog/_convert.pyc +${PYSITELIB}/myhdl/_toVerilog/_convert.pyo +${PYSITELIB}/myhdl/_traceSignals.py +${PYSITELIB}/myhdl/_traceSignals.pyc +${PYSITELIB}/myhdl/_traceSignals.pyo +${PYSITELIB}/myhdl/_unparse.py +${PYSITELIB}/myhdl/_unparse.pyc +${PYSITELIB}/myhdl/_unparse.pyo +${PYSITELIB}/myhdl/_util.py +${PYSITELIB}/myhdl/_util.pyc +${PYSITELIB}/myhdl/_util.pyo +@dirrm ${PYSITELIB}/myhdl/_toVerilog @dirrm ${PYSITELIB}/myhdl |