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| author | drochner <drochner@pkgsrc.org> | 2006-02-10 16:06:46 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2006-02-10 16:06:46 +0000 |
| commit | 4ca0722c59c3c3cc367a0360212dba8a64731f44 (patch) | |
| tree | 1d870de43aaadffb33488a8b72aaf165b69119cf /cad/py-MyHDL/PLIST | |
| parent | 123d8ca9fefd300f362fb9eb9a077cd14f3d17ae (diff) | |
| download | pkgsrc-4ca0722c59c3c3cc367a0360212dba8a64731f44.tar.gz | |
update to 0.5
major changes:
-supports Python decorator syntax for generators (needs 2.4)
-intbv() doesn't have a default anymore
-many improvements to Verilog conversion
Diffstat (limited to 'cad/py-MyHDL/PLIST')
| -rw-r--r-- | cad/py-MyHDL/PLIST | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST index 89d54ecf890..e2b0d1b1eb4 100644 --- a/cad/py-MyHDL/PLIST +++ b/cad/py-MyHDL/PLIST @@ -1,4 +1,4 @@ -@comment $NetBSD: PLIST,v 1.3 2005/01/05 15:20:10 drochner Exp $ +@comment $NetBSD: PLIST,v 1.4 2006/02/10 16:06:46 drochner Exp $ ${PYSITELIB}/myhdl/_Cosimulation.py ${PYSITELIB}/myhdl/_Cosimulation.pyc ${PYSITELIB}/myhdl/_Cosimulation.pyo @@ -14,6 +14,9 @@ ${PYSITELIB}/myhdl/_Waiter.pyo ${PYSITELIB}/myhdl/__init__.py ${PYSITELIB}/myhdl/__init__.pyc ${PYSITELIB}/myhdl/__init__.pyo +${PYSITELIB}/myhdl/_always.py +${PYSITELIB}/myhdl/_always.pyc +${PYSITELIB}/myhdl/_always.pyo ${PYSITELIB}/myhdl/_always_comb.py ${PYSITELIB}/myhdl/_always_comb.pyc ${PYSITELIB}/myhdl/_always_comb.pyo @@ -35,6 +38,9 @@ ${PYSITELIB}/myhdl/_enum.pyo ${PYSITELIB}/myhdl/_extractHierarchy.py ${PYSITELIB}/myhdl/_extractHierarchy.pyc ${PYSITELIB}/myhdl/_extractHierarchy.pyo +${PYSITELIB}/myhdl/_instance.py +${PYSITELIB}/myhdl/_instance.pyc +${PYSITELIB}/myhdl/_instance.pyo ${PYSITELIB}/myhdl/_intbv.py ${PYSITELIB}/myhdl/_intbv.pyc ${PYSITELIB}/myhdl/_intbv.pyo @@ -68,5 +74,8 @@ ${PYSITELIB}/myhdl/_unparse.pyo ${PYSITELIB}/myhdl/_util.py ${PYSITELIB}/myhdl/_util.pyc ${PYSITELIB}/myhdl/_util.pyo +${PYSITELIB}/myhdl/test.py +${PYSITELIB}/myhdl/test.pyc +${PYSITELIB}/myhdl/test.pyo @dirrm ${PYSITELIB}/myhdl/_toVerilog @dirrm ${PYSITELIB}/myhdl |