diff options
author | drochner <drochner@pkgsrc.org> | 2011-04-13 14:47:18 +0000 |
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committer | drochner <drochner@pkgsrc.org> | 2011-04-13 14:47:18 +0000 |
commit | 9c876f9e4392ac018f96becff1f6c1c7294a3beb (patch) | |
tree | 478e3bcb3442e37a57db50e0e298fa86d5aae2be /cad/py-MyHDL | |
parent | 677d2ebfa70913a45ebb34d2ef6ed0ecbf763c58 (diff) | |
download | pkgsrc-9c876f9e4392ac018f96becff1f6c1c7294a3beb.tar.gz |
update to 0.7
too many changes to list here, see the release notes
Diffstat (limited to 'cad/py-MyHDL')
-rw-r--r-- | cad/py-MyHDL/Makefile | 10 | ||||
-rw-r--r-- | cad/py-MyHDL/PLIST | 41 | ||||
-rw-r--r-- | cad/py-MyHDL/distinfo | 8 |
3 files changed, 37 insertions, 22 deletions
diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile index a9584a2dd83..2c337ee2fce 100644 --- a/cad/py-MyHDL/Makefile +++ b/cad/py-MyHDL/Makefile @@ -1,8 +1,8 @@ -# $NetBSD: Makefile,v 1.15 2008/06/12 02:14:16 joerg Exp $ +# $NetBSD: Makefile,v 1.16 2011/04/13 14:47:18 drochner Exp $ # -DISTNAME= myhdl-0.5.1 -PKGNAME= ${PYPKGPREFIX}-MyHDL-0.5.1 +DISTNAME= myhdl-0.7 +PKGNAME= ${PYPKGPREFIX}-MyHDL-0.7 CATEGORIES= cad python MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/} @@ -13,10 +13,10 @@ COMMENT= Hardware description in Python PKG_DESTDIR_SUPPORT= user-destdir PYDISTUTILSPKG= yes -PYTHON_VERSIONS_ACCEPTED= 25 24 +PYTHON_VERSIONS_ACCEPTED= 26 27 do-test: - cd ${WRKSRC}/myhdl/test && ${PYTHONBIN} test_all.py + cd ${WRKSRC}/myhdl/test/core && ${PYTHONBIN} test_all.py .include "../../lang/python/extension.mk" .include "../../mk/bsd.pkg.mk" diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST index bd5b64eda0e..c3197760143 100644 --- a/cad/py-MyHDL/PLIST +++ b/cad/py-MyHDL/PLIST @@ -1,7 +1,10 @@ -@comment $NetBSD: PLIST,v 1.6 2009/06/14 17:35:55 joerg Exp $ +@comment $NetBSD: PLIST,v 1.7 2011/04/13 14:47:18 drochner Exp $ ${PYSITELIB}/myhdl/_Cosimulation.py ${PYSITELIB}/myhdl/_Cosimulation.pyc ${PYSITELIB}/myhdl/_Cosimulation.pyo +${PYSITELIB}/myhdl/_ShadowSignal.py +${PYSITELIB}/myhdl/_ShadowSignal.pyc +${PYSITELIB}/myhdl/_ShadowSignal.pyo ${PYSITELIB}/myhdl/_Signal.py ${PYSITELIB}/myhdl/_Signal.pyc ${PYSITELIB}/myhdl/_Signal.pyo @@ -44,9 +47,6 @@ ${PYSITELIB}/myhdl/_instance.pyo ${PYSITELIB}/myhdl/_intbv.py ${PYSITELIB}/myhdl/_intbv.pyc ${PYSITELIB}/myhdl/_intbv.pyo -${PYSITELIB}/myhdl/_isGenSeq.py -${PYSITELIB}/myhdl/_isGenSeq.pyc -${PYSITELIB}/myhdl/_isGenSeq.pyo ${PYSITELIB}/myhdl/_join.py ${PYSITELIB}/myhdl/_join.pyc ${PYSITELIB}/myhdl/_join.pyo @@ -56,21 +56,36 @@ ${PYSITELIB}/myhdl/_misc.pyo ${PYSITELIB}/myhdl/_simulator.py ${PYSITELIB}/myhdl/_simulator.pyc ${PYSITELIB}/myhdl/_simulator.pyo -${PYSITELIB}/myhdl/_toVerilog/__init__.py -${PYSITELIB}/myhdl/_toVerilog/__init__.pyc -${PYSITELIB}/myhdl/_toVerilog/__init__.pyo -${PYSITELIB}/myhdl/_toVerilog/_analyze.py -${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc -${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo -${PYSITELIB}/myhdl/_toVerilog/_convert.py -${PYSITELIB}/myhdl/_toVerilog/_convert.pyc -${PYSITELIB}/myhdl/_toVerilog/_convert.pyo ${PYSITELIB}/myhdl/_traceSignals.py ${PYSITELIB}/myhdl/_traceSignals.pyc ${PYSITELIB}/myhdl/_traceSignals.pyo +${PYSITELIB}/myhdl/_tristate.py +${PYSITELIB}/myhdl/_tristate.pyc +${PYSITELIB}/myhdl/_tristate.pyo ${PYSITELIB}/myhdl/_unparse.py ${PYSITELIB}/myhdl/_unparse.pyc ${PYSITELIB}/myhdl/_unparse.pyo ${PYSITELIB}/myhdl/_util.py ${PYSITELIB}/myhdl/_util.pyc ${PYSITELIB}/myhdl/_util.pyo +${PYSITELIB}/myhdl/conversion/__init__.py +${PYSITELIB}/myhdl/conversion/__init__.pyc +${PYSITELIB}/myhdl/conversion/__init__.pyo +${PYSITELIB}/myhdl/conversion/_analyze.py +${PYSITELIB}/myhdl/conversion/_analyze.pyc +${PYSITELIB}/myhdl/conversion/_analyze.pyo +${PYSITELIB}/myhdl/conversion/_misc.py +${PYSITELIB}/myhdl/conversion/_misc.pyc +${PYSITELIB}/myhdl/conversion/_misc.pyo +${PYSITELIB}/myhdl/conversion/_toVHDL.py +${PYSITELIB}/myhdl/conversion/_toVHDL.pyc +${PYSITELIB}/myhdl/conversion/_toVHDL.pyo +${PYSITELIB}/myhdl/conversion/_toVHDLPackage.py +${PYSITELIB}/myhdl/conversion/_toVHDLPackage.pyc +${PYSITELIB}/myhdl/conversion/_toVHDLPackage.pyo +${PYSITELIB}/myhdl/conversion/_toVerilog.py +${PYSITELIB}/myhdl/conversion/_toVerilog.pyc +${PYSITELIB}/myhdl/conversion/_toVerilog.pyo +${PYSITELIB}/myhdl/conversion/_verify.py +${PYSITELIB}/myhdl/conversion/_verify.pyc +${PYSITELIB}/myhdl/conversion/_verify.pyo diff --git a/cad/py-MyHDL/distinfo b/cad/py-MyHDL/distinfo index f1d03eae860..397fd604414 100644 --- a/cad/py-MyHDL/distinfo +++ b/cad/py-MyHDL/distinfo @@ -1,5 +1,5 @@ -$NetBSD: distinfo,v 1.5 2006/05/04 16:58:05 drochner Exp $ +$NetBSD: distinfo,v 1.6 2011/04/13 14:47:18 drochner Exp $ -SHA1 (myhdl-0.5.1.tar.gz) = 4c98248be79ebb1a2c5de78aefd6c55c0675e47d -RMD160 (myhdl-0.5.1.tar.gz) = 9802663d82c86098694d34783b7352e6f5435b20 -Size (myhdl-0.5.1.tar.gz) = 768479 bytes +SHA1 (myhdl-0.7.tar.gz) = 4382444230297593f0a08ba8178c542b4ce1f19b +RMD160 (myhdl-0.7.tar.gz) = c525b21a86c9204ec7cf659709bc0e8fb2c7450b +Size (myhdl-0.7.tar.gz) = 241770 bytes |