update to verilog-current-20000805. Changes since the last packaged snapshot

are (from the authors announcements):

--------------------------------
Icarus Verilog snapshot 20000721
--------------------------------
(first snapshot after the 0.3 release)

This snapshot adds no new features or language support, but is working
towards more precise interpretation of scheduling and value propagation
details.

The first thing I've done is redesign the internal Link structure that
is used to connect the internal netlist together. There are some aspects
of the nexos of a set of links that were carried by the Link class or
by external functions. These have been moved to the new Nexus class and
linking and structure has improved because of it.

This has led me to modify the handing of signal initial values. In practice,
the time-0 value of a net is a property of the nexus instead of the objects
that are connected together, so I have implemented it so, and in the
process fixed a bunch of initial value problems.

One new feature that is added is support for non-constant delay expressions.
Now, you can even have something like ``#($random%256) <statement>'' and
expect it to do what you think. (So now the telephone example in James
Lee's "Verilog Qickstart" actually works!)

I've added some missing support for various operators in constant expressions.
I've also added some more of the friends of $random for those folks who
do stochastic modeling.

Constant propagation carries some new bug fixes, and some new smarts. It
is for example able to detect a mux with a constant 'bz input and replace
it with bufif devices, and other clevernesses with logic reduction.

--------------------------------
Icarus Verilog snapshot 20000729
--------------------------------

Like I said, the `timescale compiler directive now more or less works.
You can now specify timescale for modules, and the compiler will figure
out a global design resolution and scale your time values to match. The
VCD dumps should reflect the chosen resolution automatically. Floating
point notation is not yet supported, we'll see if that turns out to be
a problem.

A problem with `timescale support is that the compiler will allow unitless
modules. This can happen if you have `timescale late in the source file.
The default unit is the not-very-intuitive 1s. Frankly, I don't like the
`timescale semantics for this sort of reason, but its an accepted
standard, so I'm stuck with it.

I've also added support for min:typ:max expressions. The compiler chooses
one of the three expressions at compile time, based on a compile time
switch. You can ask for min typ or max values via the "-Tmin" etc. switch
to the iverilog command. If you do not specify a switch, the compiler will
choose the typ values but print warnings. The -Ttyp switch will suppress
the warnings.

I have fixed yet more net initialization bugs. These are getting pretty
subtle, now, so you should have a hard time tickling any remaining errors
here. I've also fixed a nasty and subtle bug in event expression support.
This bug only happened when the design had many event expressions with
many conjunctions.

Although they are not ready for use, I have made some forward progress
with disable statements. I now at least elaborate them, so now I just need
to figure out how to make the run-time work out. That's the hard part,
I'm afraid.

--------------------------------
Icarus Verilog snapshot 20000805
--------------------------------
I've finally dealt with a problem that's been nagging at me for a while.
Until now, it has been possible that excessively clever hierarchical
references into and out of task scopes could confound symbol lookup.
I think I finally put that to rest, and in the process reorganized the
netlist format for holding task definitions. It should no longer be
possible to confuse name binding in Icarus Verilog.

Found and fixed a silly bug in elaborating  e?a:'bz and e?'bz:a expressions
into bufifN devices. I got the sense of the enable wrong in one of the
cases. All fixed (and the test suite updated to catch this silly mistake:-)

tri0 and tri1 nets should now work properly. These are mostly a run-
time issue which I solved using resolution functions. This is actually
a technique that I borrowed from VHDL.

For those of you doing XNF synthesis, I fixed up my FF/RAM detector to
allow <= assignments in always blocks. This is in fact the preferred way
to describe DFFs as <= more accurately simulates their RTL nature.

Also found and fixed a few DOS \r\n line end issues in the lexical ana-
lyser and the preprocessor. We sometimes forget how tricky these line-
end problems can be, and compiler directives are the most susceptible.
This problem most likely occurs when you transport files from a DOS
environment. (The MAC folks haven't complained much, so either I got it
right for them, or Kato took care of the problems for me:-)

1 files changed, 3 insertions, 3 deletions

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index d492df913f6..13efab7a276 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.6 2000/05/30 23:43:43 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.7 2000/08/06 15:43:34 dmcmahill Exp $
 #
 
-DISTNAME=	verilog-20000527
-PKGNAME=	verilog-current-20000527
+DISTNAME=	verilog-20000805
+PKGNAME=	verilog-current-20000805
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/