update to verilog-current-20000409.

changes since the last packaged snapshot include:


Icarus Verilog 20000326 Snapshot:
--------------------------------
The VVM backend rewrite continues. More templates are gone, and the
bit functions have been pretty much rewritten. The vvm library now handles
bit values with strengths, and most of the devices to the right things
with those strengths.

The most obvious implication of this is that you can write multiple
drivers to a net and expect the values to be properly resolved, and in
particular the HiZ value works as it should. So I am well on the way to
completing strength modeling support.

What is still missing is support for strength specifications in the
Verilog source. Although the parser supports the strength related keywords,
they are not passed on to elaboration, or used to generate drivers with
the proper strengths. So that's in the works.

While doing all this VVM rewrite, I've made the generated code considerably
smaller. And of course fewer templates are used. The upshot of this is that
compiles of larger designs should go a whole lot faster. This is important
because people are using Icarus Verilog for increasingly larger designs.
On some larger examples, I've achieved more then 3X compile time improvement.

Icarus Verilog 20000409 Snapshot:
--------------------------------
Named events now work!  Event object declarations and trigger statements
are fully supported, and blocking on a single event also works. I'm not
up to named events in event lists because I'm in the midst of redesigning
the way events on nets and regs are implemented. However, the common case
works fine, so there you are.

I've also added support for some more arithmetic operators. Division and
Modulus now work in many contexts, and are not far from working everywhere.
Also, comparison operators work in places they used to not.

There was a compile error in memory objects that managed to slip through
a couple snapshots, that I finally cured. The problem was pretty gross,
but somehow not quite tickled by my tests. Oh well.

I've integrated some VCD improvements from Anthony Bybell. Some of you
recognize the name as the author of GTKWave, so if he says VCD works like
so, then that's how VCD works:-) Anyhow, he fixed the VCD output to be
more portable, and also a bit smaller when vectors are involved. He also
fixed some bugs with multiple calls to $dumpvars.

1 files changed, 3 insertions, 3 deletions

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index c5131f53f03..91a0b68399b 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.2 2000/03/25 21:09:16 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.3 2000/04/09 23:11:49 dmcmahill Exp $
 #
 
-DISTNAME=	verilog-20000318
-PKGNAME=	verilog-current-20000318
+DISTNAME=	verilog-20000409
+PKGNAME=	verilog-current-20000409
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/