update to verilog-current-20021019

Release Notes for Icarus Verilog Snapshot 20021019

The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.

The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.

The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.

The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.

Rearrange some of the configure script tests to assure better
compatibility accross platforms.

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