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| author | drochner <drochner@pkgsrc.org> | 2003-08-25 11:21:50 +0000 |
|---|---|---|
| committer | drochner <drochner@pkgsrc.org> | 2003-08-25 11:21:50 +0000 |
| commit | 8eb9dd370110f5be0f08124e42f85d2b268c3ce8 (patch) | |
| tree | 311c13f5c482acf3b942bd5a62625a6267f55ef2 /cad/verilog-current/distinfo | |
| parent | 4d6d5d73b3461001d3e711382e4c71e22673327d (diff) | |
| download | pkgsrc-8eb9dd370110f5be0f08124e42f85d2b268c3ce8.tar.gz | |
update to the 20030815 shapshot
changes are basically bugfixes, and improvements in the FPGA synthesis
area
Diffstat (limited to 'cad/verilog-current/distinfo')
| -rw-r--r-- | cad/verilog-current/distinfo | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index 5273729016b..85ffe0f5525 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,5 +1,5 @@ -$NetBSD: distinfo,v 1.17 2003/07/14 09:51:48 drochner Exp $ +$NetBSD: distinfo,v 1.18 2003/08/25 11:21:50 drochner Exp $ -SHA1 (verilog-20030705.tar.gz) = 1f6d0284b8efa63441e8b2650d11df434a48f374 -Size (verilog-20030705.tar.gz) = 910118 bytes +SHA1 (verilog-20030815.tar.gz) = 64ee9ca573882fd2a414fc62ee17302fc0bca26e +Size (verilog-20030815.tar.gz) = 1246700 bytes SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a |