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| author | dmcmahill <dmcmahill@pkgsrc.org> | 2000-03-25 21:09:16 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2000-03-25 21:09:16 +0000 |
| commit | eb6957f23250b9cfacd72de9a5e37f9231820825 (patch) | |
| tree | 9ae2d8a6daeb8a912d1179528bde5f3702a96bf0 /cad/verilog-current/files/patch-sum | |
| parent | a9432e7ef01c73fa5e91b15b5f01f4483f4a0718 (diff) | |
| download | pkgsrc-eb6957f23250b9cfacd72de9a5e37f9231820825.tar.gz | |
Update to verilog-current-20000318.
Notable changes since the last pkg are (from the snapshot announcement):
Parameters are complete.
What this means is that I finally got around to supporting defparam,
and while I was at it I rewrote the entire parameter handling and added
the parameter support included in 1364-2000.
I have rewritten major portions of the VVM backend. The vvm_nexus class
has been introduced to the fray, and all the device implementations in
the VVM library now use the nexus to drive and receive values. An advantage
of this scheme is that the t-vvm backend code (in ivl proper) is simpler,
and so is the generated C++ code.
I also removed most of the template classes. This proved to be a huge
compile-time benefit (though compiling twice as fast really only matters
for large programs) and it doesn't seem likely to hurt run-time performance.
A few remain, either because they seemed harmless (the N-wide logic gates)
or I couldn't yet figure out a good way to replace them (vvm_bitset_t).
A side benefit of this is that the vvm library may now be a modeling
library that ordinary humans can use to write their models in C++. This
may provide the unexpected benefit of heading me towards incremental
compilation of designs. So who was it who was beating me over the head
asking for that?-)
I also fixed a few minor problems with the preprocessor. Those of you
who reported problems with `includes and `defines should check this out.
Diffstat (limited to 'cad/verilog-current/files/patch-sum')
| -rw-r--r-- | cad/verilog-current/files/patch-sum | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum index b748dbed2d9..b5a0eb74787 100644 --- a/cad/verilog-current/files/patch-sum +++ b/cad/verilog-current/files/patch-sum @@ -1,4 +1,4 @@ -$NetBSD: patch-sum,v 1.2 2000/03/07 20:36:51 dmcmahill Exp $ +$NetBSD: patch-sum,v 1.3 2000/03/25 21:09:16 dmcmahill Exp $ -MD5 (patch-ad) = 35aae681e397bc9d5be0f6765a8adc96 +MD5 (patch-ad) = 1c410a390d7fd9b9db96b933926b30ee MD5 (patch-ae) = 44921f529c17458cd3ba34d35dc0da77 |