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authordmcmahill <dmcmahill@pkgsrc.org>2002-03-28 03:07:29 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2002-03-28 03:07:29 +0000
commit06c065be8c21f03801d49a0050e4abdb32c21dd1 (patch)
tree7a3d4a27fa9268a56ce0e6100b93ede4646db2e3 /cad/verilog-current
parent6c0f70478632f12ba9b5d51d98a156641b1516e8 (diff)
downloadpkgsrc-06c065be8c21f03801d49a0050e4abdb32c21dd1.tar.gz
update to verilog-current-20020317
Release Notes for snapshot 20020317 The first difference in this snapshot from the 0.6 release is that vvm is no longer compiled by default. If you want to compile vvm, you must enable it at configure time (--enable-vvm) and rebuild from scratch. Eventually, vvm will disappear from the release altogether. The next major difference is new support for user defined functions. It is new support, so it is bound to be buggy, but it should be somewhat complete. The major problem has been solved, so all that remains are bugs around the edges. The vvp run-time scheduler has been changed slightly. The run time behavior is getting increasingly precise and picky, as larger designs are thrown at the compiler. The change introduced in this snapshot fixes logic gates to not propagate zero-time pulses, and thus fixes some weird bugs in large designs. I've also added initial support for the Verilog 200x pragma comment, which are (* *) pairs. For now, the compiler ignores them as comments. This is what a compiler is supposed to do with anything that is not specifically recognized. Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output file is a waveform output format that is much more compact then VCD. The gtkwave waveform viewer supports the LXT format, and should operate a bit faster when viewing LXT files. For now, there are separate system tasks for managing LXT output ($lxt_dumpvars, etc) but eventually the dump format will be selectable by environment variable or command line switch. This snapshot also includes various random bug fixes and improved error messages for incorrect code.
Diffstat (limited to 'cad/verilog-current')
-rw-r--r--cad/verilog-current/Makefile7
-rw-r--r--cad/verilog-current/PLIST10
-rw-r--r--cad/verilog-current/distinfo6
3 files changed, 8 insertions, 15 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 290892faf5b..0331d1b11a4 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,9 @@
-# $NetBSD: Makefile,v 1.24 2002/01/16 19:33:18 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.25 2002/03/28 03:07:29 dmcmahill Exp $
#
-DISTNAME= verilog-20020112
-PKGNAME= verilog-current-20020112
+DISTNAME= verilog-${SNAPDATE}
+PKGNAME= verilog-current-${SNAPDATE}
+SNAPDATE= 20020317
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
diff --git a/cad/verilog-current/PLIST b/cad/verilog-current/PLIST
index ec202cb99f5..97f3a394595 100644
--- a/cad/verilog-current/PLIST
+++ b/cad/verilog-current/PLIST
@@ -1,19 +1,11 @@
-@comment $NetBSD: PLIST,v 1.1 2001/11/01 00:49:38 zuntum Exp $
+@comment $NetBSD: PLIST,v 1.2 2002/03/28 03:07:29 dmcmahill Exp $
bin/iverilog
bin/vvp
include/ivl_target.h
include/vpi_priv.h
include/vpi_user.h
-include/vvm.h
-include/vvm_calltf.h
-include/vvm_func.h
-include/vvm_gates.h
-include/vvm_nexus.h
-include/vvm_signal.h
-include/vvm_thread.h
lib/libvpi.a
lib/libvpip.a
-lib/libvvm.a
lib/ivl/fpga.tgt
lib/ivl/ivl
lib/ivl/iverilog.conf
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index 48d28f1ac47..3505c81ce67 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.8 2002/01/16 19:33:18 dmcmahill Exp $
+$NetBSD: distinfo,v 1.9 2002/03/28 03:07:29 dmcmahill Exp $
-SHA1 (verilog-20020112.tar.gz) = 0e07f73cf7514a2d669a63b5990562a41dd0d85a
-Size (verilog-20020112.tar.gz) = 719621 bytes
+SHA1 (verilog-20020317.tar.gz) = ed654587e73d6a6c9a987784e5905b3c7c52d974
+Size (verilog-20020317.tar.gz) = 744554 bytes
SHA1 (patch-ad) = 3c035d32d011d81520e428e3dd9adae435fc63e7