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authordmcmahill <dmcmahill@pkgsrc.org>2002-08-29 11:15:56 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2002-08-29 11:15:56 +0000
commit04b0aa23bf2bbd2c2c4674caaf96f7901d59afa0 (patch)
tree3972dac8b6730ea352813ee95ce854f9cc431abc /cad/verilog-current
parent018332daf1756036609d636261ab219f1493b523 (diff)
downloadpkgsrc-04b0aa23bf2bbd2c2c4674caaf96f7901d59afa0.tar.gz
update to verilog-current-20020828
Release Notes for Snapshot 20020828 This snapshot adds support for parameter and localparam bit ranges. This is a IEEE1364-2001 feature, although some -1995 compilers have supported it in the past. Fixed a *nasty* and slippery bug with the evaluation of bit select of nets. (Bit select of variables was unaffected.) The symptoms did not clearly point to the problem, so bugs related to it were often mis- reported. Gate delays were lost when constants were propagated to their inputs. This is fixed for the known broken cases. Also, mux output delays have been fixed. Also, release statements that apply to elided nets are turned into no-ops. The r-values of non-blocking assignments are now precalculated at compile time, if possible, as is done with blocking assignments. This speeds up constant propagation, and is more thorough. Also optimize subtraction of small constants from vectors, with the new %subi instruction in vvp. This saves some in code size and thread footprint. Handling of x in r-value bit selects and memory word selects did the wrong thing. Now they do the right thing. Also, x in the selector of ?: ternary operators does the right (and complicated) thing now. In the process, a fork-join code generator bug was fixed. Several bugs with time formatting have been fixed. Temporaries in sequential blocks are detected by the synthesizer, and converted into wires when needed. This expands support for combinational logic synthesis.
Diffstat (limited to 'cad/verilog-current')
-rw-r--r--cad/verilog-current/Makefile4
-rw-r--r--cad/verilog-current/distinfo6
2 files changed, 5 insertions, 5 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index fdc49d84380..50cc48971b0 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,9 +1,9 @@
-# $NetBSD: Makefile,v 1.27 2002/08/24 04:36:44 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.28 2002/08/29 11:15:56 dmcmahill Exp $
#
DISTNAME= verilog-${SNAPDATE}
PKGNAME= verilog-current-${SNAPDATE}
-SNAPDATE= 20020817
+SNAPDATE= 20020828
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index dd1df738c86..0720c16f7b9 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.11 2002/08/24 04:36:45 dmcmahill Exp $
+$NetBSD: distinfo,v 1.12 2002/08/29 11:15:57 dmcmahill Exp $
-SHA1 (verilog-20020817.tar.gz) = 61170d811c5c7eafbe7f05007ac4010a51c81f68
-Size (verilog-20020817.tar.gz) = 809419 bytes
+SHA1 (verilog-20020828.tar.gz) = 19fb0e1e9f22b9819d2369aca370fb806381bb3d
+Size (verilog-20020828.tar.gz) = 815247 bytes
SHA1 (patch-ad) = 610a4b597b056f4e951cb75bdb13a9370efec300