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author | dmcmahill <dmcmahill@pkgsrc.org> | 2000-05-10 23:19:00 +0000 |
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committer | dmcmahill <dmcmahill@pkgsrc.org> | 2000-05-10 23:19:00 +0000 |
commit | 9f9f676ac4c8b4fd64cd467e0cce67341cee3728 (patch) | |
tree | c94a31442ac5e004a34bd02be9a68ede0d9d67f4 /cad/verilog-current | |
parent | 1d9cc6cbcd96a23ce9e94cd860806e9f5a53fbf9 (diff) | |
download | pkgsrc-9f9f676ac4c8b4fd64cd467e0cce67341cee3728.tar.gz |
distinguish these 2 packages as "development snapshot" and "released" so
its more obvious of the difference.
Diffstat (limited to 'cad/verilog-current')
-rw-r--r-- | cad/verilog-current/pkg/COMMENT | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/verilog-current/pkg/COMMENT b/cad/verilog-current/pkg/COMMENT index 1762c44bef6..7b69985783c 100644 --- a/cad/verilog-current/pkg/COMMENT +++ b/cad/verilog-current/pkg/COMMENT @@ -1 +1 @@ -Verilog simulation and synthesis tool +Verilog simulation and synthesis tool (development snapshot version) |