diff options
| author | dmcmahill <dmcmahill@pkgsrc.org> | 2004-06-07 01:09:50 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2004-06-07 01:09:50 +0000 |
| commit | 4970d0ff3f27a5038e42d32251c65c065cb32e80 (patch) | |
| tree | ddad9a76788fe6962c11dca70cf40cf8c1275183 /cad/verilog-current | |
| parent | d8c16214b19a82635f88cf21612f59d41d738596 (diff) | |
| download | pkgsrc-4970d0ff3f27a5038e42d32251c65c065cb32e80.tar.gz | |
update to verilog-current-20040606
* Release Notes for Icarus Verilog Snapshot 20040606
Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.
System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.
Non-blocking assign of real values to real variables now works.
Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.
Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.
Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.
Handle Negative value reals, and a few other bugs related to real
numbers.
Change internal use of identifiers to perm_strings for better
performance.
Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.
Better compile-time support for Cygwin vs mingw32.
The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)
Diffstat (limited to 'cad/verilog-current')
| -rw-r--r-- | cad/verilog-current/Makefile | 4 | ||||
| -rw-r--r-- | cad/verilog-current/distinfo | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index 02387d79fb0..3dccf1ad3f3 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.39 2004/03/22 00:15:07 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.40 2004/06/07 01:09:50 dmcmahill Exp $ # DISTNAME= verilog-${SNAPDATE} @@ -18,7 +18,7 @@ USE_BUILDLINK3= yes BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison BUILD_DEPENDS+= gperf>=2.7.2:../../devel/gperf -SNAPDATE= 20040220 +SNAPDATE= 20040606 GNU_CONFIGURE= yes USE_GNU_TOOLS+= lex make CONFIGURE_ARGS+= --without-ipal diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index 18d3f03e2d8..e7570f80254 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,5 +1,5 @@ -$NetBSD: distinfo,v 1.19 2004/03/02 15:34:07 drochner Exp $ +$NetBSD: distinfo,v 1.20 2004/06/07 01:09:50 dmcmahill Exp $ -SHA1 (verilog-20040220.tar.gz) = 22b09fced8cbc5cc0665574d03595aa367ccdb3b -Size (verilog-20040220.tar.gz) = 1354505 bytes +SHA1 (verilog-20040606.tar.gz) = f91dc4c6e93eef13fab6dbc80144ed48c633d1eb +Size (verilog-20040606.tar.gz) = 1361219 bytes SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a |