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| author | dmcmahill <dmcmahill@pkgsrc.org> | 2006-01-25 12:11:00 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2006-01-25 12:11:00 +0000 |
| commit | 7db586530d48bab2cc6afba8c2d8c147d905a353 (patch) | |
| tree | 1ae7b6699db5016b040ed93b378c4e0cb120313d /cad/verilog-current | |
| parent | f350bb883465caf1d7fdffb3e5e5ffcfdaa64d02 (diff) | |
| download | pkgsrc-7db586530d48bab2cc6afba8c2d8c147d905a353.tar.gz | |
update to 20060124 snapshot.
A few new features have been added to allow proper simulation with
newer Xilinx UNISIM models. (They are starting to use Verilog 2001
features.) And also various bug fixes in this release.
-- Primitive and continuous assign delays can now be non-constant. This
needed some new run-time support, so vvp had a slight format change,
and certain new optimizations follow as a result.
-- Bug handling certain constant sub-expressions in concatenation
expressions. Also, allow concat expressions in constant contexts.
-- Support for wide divide expressions.
-- Fixes for stubborn compilers.
-- Fix bugs in padding of signed expressions.
-- More fixes for following the data types of expressions.
Diffstat (limited to 'cad/verilog-current')
| -rw-r--r-- | cad/verilog-current/Makefile | 6 | ||||
| -rw-r--r-- | cad/verilog-current/PLIST | 6 | ||||
| -rw-r--r-- | cad/verilog-current/distinfo | 8 |
3 files changed, 8 insertions, 12 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index d11cc15c710..5b26db0a817 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,10 +1,10 @@ -# $NetBSD: Makefile,v 1.48 2005/05/22 20:28:47 jlam Exp $ +# $NetBSD: Makefile,v 1.49 2006/01/25 12:11:00 dmcmahill Exp $ # DISTNAME= verilog-${SNAPDATE} PKGNAME= verilog-current-${SNAPDATE} CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/pre-0.8/ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ MAINTAINER= dmcmahill@NetBSD.org HOMEPAGE= http://icarus.com/eda/verilog/index.html @@ -14,7 +14,7 @@ PKG_INSTALLATION_TYPES= overwrite pkgviews CONFLICTS+= verilog-[0-9]* -SNAPDATE= 20041004 +SNAPDATE= 20060124 GNU_CONFIGURE= yes USE_TOOLS+= bison gmake lex CONFIGURE_ARGS+= --without-ipal diff --git a/cad/verilog-current/PLIST b/cad/verilog-current/PLIST index 52075cb0820..edceef6ce75 100644 --- a/cad/verilog-current/PLIST +++ b/cad/verilog-current/PLIST @@ -1,4 +1,4 @@ -@comment $NetBSD: PLIST,v 1.7 2004/09/02 01:55:47 dmcmahill Exp $ +@comment $NetBSD: PLIST,v 1.8 2006/01/25 12:11:01 dmcmahill Exp $ bin/iverilog bin/iverilog-vpi bin/vvp @@ -10,9 +10,6 @@ include/vpi_user.h lib/libveriuser.a lib/libvpi.a lib/ivl/cadpli.vpl -lib/ivl/fpga-s.conf -lib/ivl/fpga.conf -lib/ivl/fpga.tgt lib/ivl/ivl lib/ivl/ivlpp lib/ivl/null-s.conf @@ -26,7 +23,6 @@ lib/ivl/vvp.tgt lib/ivl/xnf-s.conf lib/ivl/xnf.conf man/man1/iverilog.1 -man/man1/iverilog-fpga.1 man/man1/iverilog-vpi.1 man/man1/vvp.1 @dirrm lib/ivl diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index 133f67b64de..b9709dd2946 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,6 +1,6 @@ -$NetBSD: distinfo,v 1.24 2005/02/23 14:59:25 agc Exp $ +$NetBSD: distinfo,v 1.25 2006/01/25 12:11:01 dmcmahill Exp $ -SHA1 (verilog-20041004.tar.gz) = 820763bbf1f5e3f001f73e195d274be76b8ae0a4 -RMD160 (verilog-20041004.tar.gz) = a8cf81f67b86d930f055e276d41589cbef71c003 -Size (verilog-20041004.tar.gz) = 1371537 bytes +SHA1 (verilog-20060124.tar.gz) = 4b3784aeb5b91c0672522cd420dd96e73bd4e33c +RMD160 (verilog-20060124.tar.gz) = de536f3d9c811dbbeea36bb64007aa26355dddcb +Size (verilog-20060124.tar.gz) = 1507887 bytes SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a |