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| author | dmcmahill <dmcmahill@pkgsrc.org> | 2001-08-04 01:20:43 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2001-08-04 01:20:43 +0000 |
| commit | 0bdc96ae111e5f50e46f8341b653f069051e331d (patch) | |
| tree | fb7a953d710d8aa2d602e08e725f2c97f6431ec6 /cad/verilog/Makefile | |
| parent | 33d5f87cd4b027c69e7fa9640fb6aaffe15d142e (diff) | |
| download | pkgsrc-0bdc96ae111e5f50e46f8341b653f069051e331d.tar.gz | |
update to verilog-0.5
* The Big Change: VVP
Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.
The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.
The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.
There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.
* What Else Is New
The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.
Diffstat (limited to 'cad/verilog/Makefile')
| -rw-r--r-- | cad/verilog/Makefile | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index 095e0804b47..67728beb75b 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,9 +1,9 @@ -# $NetBSD: Makefile,v 1.9 2001/06/11 06:34:20 jlam Exp $ +# $NetBSD: Makefile,v 1.10 2001/08/04 01:20:43 dmcmahill Exp $ # -DISTNAME= verilog-0.4 +DISTNAME= verilog-0.5 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.4/ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.5/ MAINTAINER= dmcmahill@netbsd.org HOMEPAGE= http://icarus.com/eda/verilog/index.html @@ -11,13 +11,16 @@ COMMENT= Verilog simulation and synthesis tool (stable release version) BUILD_DEPENDS+= bison-*:../../devel/bison BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf -DEPENDS+= ipal-current>=20001210:../../cad/ipal-current +# +# turn this back on when ipal comes along a little further +#DEPENDS+= ipal-current>=20001210:../../cad/ipal-current CONFLICTS+= verilog-current-[0-9]* GNU_CONFIGURE= yes USE_GMAKE= yes # to find ipal.h: -CPPFLAGS+= -I${LOCALBASE}/include +#CPPFLAGS+= -I${LOCALBASE}/include +CONFIGURE_ARGS+= --without-ipal .include "../../mk/bsd.pkg.mk" |