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| author | dmcmahill <dmcmahill@pkgsrc.org> | 2002-12-15 01:57:12 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2002-12-15 01:57:12 +0000 |
| commit | fe2c5b1c959ebd3e093365fef8f206c2761be4c0 (patch) | |
| tree | 169374e729dd74436c02734f349cf590500a8dcf /cad/verilog/Makefile | |
| parent | 5dcda1ae5bf5f07650749fa1c4a5f83e4ca15c40 (diff) | |
| download | pkgsrc-fe2c5b1c959ebd3e093365fef8f206c2761be4c0.tar.gz | |
update to verilog-0.7
This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
Diffstat (limited to 'cad/verilog/Makefile')
| -rw-r--r-- | cad/verilog/Makefile | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index 8f50752d746..aa28bad22e8 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,9 +1,9 @@ -# $NetBSD: Makefile,v 1.12 2002/02/08 01:48:31 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.13 2002/12/15 01:57:12 dmcmahill Exp $ # -DISTNAME= verilog-0.6 +DISTNAME= verilog-0.7 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.6/ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.7/ MAINTAINER= dmcmahill@netbsd.org HOMEPAGE= http://icarus.com/eda/verilog/index.html @@ -24,10 +24,7 @@ USE_GMAKE= yes #CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}" CONFIGURE_ARGS+= --without-ipal YACC= ${LOCALBASE}/bin/bison - -test: build - cd ${WRKSRC} && \ - ${MAKE_ENV} ${MAKE_PROGRAM} check 2>&1 | \ - tee ${WRKDIR}/tests.log +TEST_DIRS= ${WRKSRC} +TEST_TARGET= check .include "../../mk/bsd.pkg.mk" |