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| author | dmcmahill <dmcmahill> | 2004-03-10 05:13:38 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill> | 2004-03-10 05:13:38 +0000 |
| commit | f62de174f3c0ec0f36d1ca32d7ac88d41e0d6329 (patch) | |
| tree | fa3eb577c63147935eba3b5ef3038a539f7fdfdf /cad/verilog/PLIST | |
| parent | 08829e0891f0d9dcdb56d17132dacb8dd62dbaf1 (diff) | |
| download | pkgsrc-f62de174f3c0ec0f36d1ca32d7ac88d41e0d6329.tar.gz | |
set F77 as well as FC.
was:
1% make show-var PKG_STAGE=configure VARNAME=FC
g77
2% make show-var PKG_STAGE=configure VARNAME=F77
/usr/pkgsrc-current/math/scilab/work/.gcc/bin/g77
is:
3% make show-var PKG_STAGE=configure VARNAME=FC
g77
4% make show-var PKG_STAGE=configure VARNAME=F77
g77
fixes some buildlink spillover noted in the scilab package.
Diffstat (limited to 'cad/verilog/PLIST')
0 files changed, 0 insertions, 0 deletions