Drop trailing whitespace. Ok'ed by wiz.

1 files changed, 2 insertions, 2 deletions

diff --git a/cad/verilog/DESCR b/cad/verilog/DESCR
index fa22179d8b0..a1f488afa95 100644
--- a/cad/verilog/DESCR
+++ b/cad/verilog/DESCR
@@ -1,10 +1,10 @@
-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a 
+Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
 compiler, compiling source code writen in Verilog (IEEE-1364) into some target
 format. For batch simulation, the compiler can generate C++ code that is
 compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.
-   
+  
 The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's