update to verilog-0.4.

from the authors announcement:

So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)

speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)

for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4

8 files changed, 31 insertions, 105 deletions

diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index 367b269df49..5a7d837c965 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,19 +1,23 @@
-# $NetBSD: Makefile,v 1.4 2000/06/22 03:15:31 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.5 2001/02/04 15:36:49 dmcmahill Exp $
 #
 
-DISTNAME=       verilog-0.3
-CATEGORIES=     cad
-MASTER_SITES=   ftp://icarus.com/pub/eda/verilog/v0.3/
+DISTNAME=	verilog-0.4
+CATEGORIES=	cad
+MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v0.4/
 
-MAINTAINER=     dmcmahill@netbsd.org
-HOMEPAGE=       http://icarus.com/eda/verilog/index.html
+MAINTAINER=	dmcmahill@netbsd.org
+HOMEPAGE=	http://icarus.com/eda/verilog/index.html
 
-BUILD_DEPENDS+= bison:../../devel/bison
+BUILD_DEPENDS+=	bison:../../devel/bison
 BUILD_DEPENDS+=	gperf:../../devel/gperf
+DEPENDS+=	ipal-current>=20001210:../../cad/ipal-current
 
-CONFLICTS+=     verilog-current
+CONFLICTS+=	verilog-current
 
 GNU_CONFIGURE=	yes
-USE_GMAKE=      yes
+USE_GMAKE=	yes
+# to find ipal.h:
+CPPFLAGS+=	-I${LOCALBASE}/include
+CONFIGURE_ENV+=	CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}"
 
 .include "../../mk/bsd.pkg.mk"
diff --git a/cad/verilog/files/md5 b/cad/verilog/files/md5
index 35a7603a908..004af9aeb74 100644
--- a/cad/verilog/files/md5
+++ b/cad/verilog/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.4 2000/06/22 03:15:32 dmcmahill Exp $
+$NetBSD: md5,v 1.5 2001/02/04 15:36:50 dmcmahill Exp $
 
-MD5 (verilog-0.3.tar.gz) = eebe52780df6adcc436942bc2de2969c
+MD5 (verilog-0.4.tar.gz) = d2b0c7c1480ffb2ad1b440bded97e419
diff --git a/cad/verilog/files/patch-sum b/cad/verilog/files/patch-sum
index e67643478e5..404604a34a4 100644
--- a/cad/verilog/files/patch-sum
+++ b/cad/verilog/files/patch-sum
@@ -1,6 +1,3 @@
-$NetBSD: patch-sum,v 1.6 2000/07/11 14:35:58 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.7 2001/02/04 15:36:50 dmcmahill Exp $
 
-MD5 (patch-aa) = b6c4526b7458f1de95c4158aaf0c74ab
-MD5 (patch-ab) = 8e1ec1875b9f1c8a969205c81598be94
-MD5 (patch-ac) = 57decd66420e549d30130616041d116e
-MD5 (patch-ad) = d875516e4fc53270d66101a60bc1e8e5
+MD5 (patch-ad) = a9da357e98b2a3ddf6572a0f51b2f5f7
diff --git a/cad/verilog/patches/patch-aa b/cad/verilog/patches/patch-aa
deleted file mode 100644
index b4e8090a6c5..00000000000
--- a/cad/verilog/patches/patch-aa
+++ /dev/null
@@ -1,14 +0,0 @@
-$NetBSD: patch-aa,v 1.3 2000/06/30 19:55:06 dmcmahill Exp $
-
-use a default timescale of 1ns instead of 1ps.  This will make the VCD output
-compatible with Dinotrace.
-
---- vpi/sys_vcd.c.orig	Fri Jun  2 22:22:15 2000
-+++ vpi/sys_vcd.c	Fri Jun 30 15:51:40 2000
-@@ -252,5 +252,5 @@
- 	    fprintf(dump_file, "$end\n");
- 	    fprintf(dump_file, "$timescale\n");
--	    fprintf(dump_file, "\t1ps\n");
-+	    fprintf(dump_file, "\t1ns\n");
- 	    fprintf(dump_file, "$end\n");
-       }
diff --git a/cad/verilog/patches/patch-ab b/cad/verilog/patches/patch-ab
deleted file mode 100644
index 8c67ee3dc79..00000000000
--- a/cad/verilog/patches/patch-ab
+++ /dev/null
@@ -1,11 +0,0 @@
-$NetBSD: patch-ab,v 1.3 2000/06/22 03:15:32 dmcmahill Exp $
-
---- vpi/Makefile.in.orig	Wed May  3 23:37:59 2000
-+++ vpi/Makefile.in	Sun Jun 11 18:59:57 2000
-@@ -42,5 +42,5 @@
- INSTALL_DATA = @INSTALL_DATA@
- 
--CPPFLAGS = @CPPFLAGS@ @DEFS@ -fpic
-+CPPFLAGS = @CPPFLAGS@ @DEFS@ -fPIC
- CXXFLAGS = @CXXFLAGS@
- LDFLAGS = @LDFLAGS@
diff --git a/cad/verilog/patches/patch-ac b/cad/verilog/patches/patch-ac
deleted file mode 100644
index 8c175941bc1..00000000000
--- a/cad/verilog/patches/patch-ac
+++ /dev/null
@@ -1,56 +0,0 @@
-$NetBSD: patch-ac,v 1.3 2000/07/11 14:36:20 dmcmahill Exp $
-
-give the correct return value
-
---- iverilog.c.orig	Fri Jun 16 15:00:06 2000
-+++ iverilog.c	Tue Jul 11 10:27:28 2000
-@@ -26,4 +26,7 @@
- #include <string.h>
- 
-+#include <sys/types.h>
-+#include <sys/wait.h>
-+
- #ifndef IVL_ROOT
- # define IVL_ROOT "."
-@@ -88,5 +91,5 @@
- 
-       rc = system(cmd);
--      return rc;
-+      return(WEXITSTATUS(rc));
- }
- 
-@@ -142,5 +145,5 @@
-       if (rc != 0) {
- 	    fprintf(stderr, "errors translating Verilog program.\n");
--	    return rc;
-+	    return(WEXITSTATUS(rc));
-       }
- 
-@@ -155,5 +158,5 @@
-       if (rc != 0) {
- 	    fprintf(stderr, "errors compiling translated program.\n");
--	    return rc;
-+	    return(WEXITSTATUS(rc));
-       }
- 
-@@ -201,5 +204,5 @@
-       rc = system(cmd);
- 
--      return rc;
-+      return(WEXITSTATUS(rc));
- }
- 
-@@ -225,4 +228,5 @@
-       int opt, idx;
-       char*cp;
-+      int rc;
- 
-       while ((opt = getopt(argc, argv, "B:D:Ef:I:m:o:Ss:t:vW:")) != EOF) {
-@@ -362,5 +366,6 @@
- 		  printf("preprocess: %s\n", cmd);
- 
--	    return system(cmd);
-+	    rc=system(cmd);
-+	    return(WEXITSTATUS(rc));
-       }
- 
diff --git a/cad/verilog/patches/patch-ad b/cad/verilog/patches/patch-ad
index ce256dfff6d..28162a65205 100644
--- a/cad/verilog/patches/patch-ad
+++ b/cad/verilog/patches/patch-ad
@@ -1,13 +1,14 @@
-$NetBSD: patch-ad,v 1.4 2000/06/22 03:15:32 dmcmahill Exp $
+$NetBSD: patch-ad,v 1.5 2001/02/04 15:36:50 dmcmahill Exp $
 
-don't use -O2 on parse.cc because of compiler bugs on sparc and pmax
-(maybe others).
+work around a c++ -O2 bug which is present on at least sparc 
+and pmax using egcs-1.1.1 
 
---- Makefile.in.orig	Fri Apr 28 12:50:53 2000
-+++ Makefile.in	Sat Apr 29 08:39:00 2000
-@@ -115,4 +115,6 @@
+--- Makefile.in.orig	Fri Dec  8 20:17:38 2000
++++ Makefile.in	Sat Dec 16 19:07:25 2000
+@@ -137,4 +137,7 @@
  
- parse.o dep/parse.d: parse.cc
+ parse.o: parse.cc
++	@[ -d dep ] || mkdir dep
 +	$(CXX) -MD -c -I. $(CPPFLAGS)  $<
 +	mv parse.d dep/parse.d
  
diff --git a/cad/verilog/pkg/PLIST b/cad/verilog/pkg/PLIST
index a0e65cb9165..b80c9050f5d 100644
--- a/cad/verilog/pkg/PLIST
+++ b/cad/verilog/pkg/PLIST
@@ -1,5 +1,6 @@
-@comment $NetBSD: PLIST,v 1.2 2000/06/22 03:15:33 dmcmahill Exp $
+@comment $NetBSD: PLIST,v 1.3 2001/02/04 15:36:51 dmcmahill Exp $
 bin/iverilog
+include/ivl_target.h
 include/vpi_priv.h
 include/vpi_user.h
 include/vvm.h
@@ -9,9 +10,13 @@ include/vvm_gates.h
 include/vvm_nexus.h
 include/vvm_signal.h
 include/vvm_thread.h
+lib/ivl/iverilog.conf
 lib/ivl/ivl
 lib/ivl/ivlpp
+lib/ivl/null.tgt
+lib/ivl/pal.tgt
 lib/ivl/system.vpi
+lib/libvpip.a
 lib/libvvm.a
 man/man1/iverilog.1
 @dirrm lib/ivl