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| author | dmcmahill <dmcmahill@pkgsrc.org> | 2002-02-08 01:48:31 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2002-02-08 01:48:31 +0000 |
| commit | 51cc1f3f79295a580f57aeede022d940cf261799 (patch) | |
| tree | 89804bc4f6c3757c085f11dac89c0ed0cff16fec /cad/verilog | |
| parent | ef357bb2e15a9f59697c1141376ecaf034a703a4 (diff) | |
| download | pkgsrc-51cc1f3f79295a580f57aeede022d940cf261799.tar.gz | |
update to verilog-0.6
WHAT'S NEW SINCE 0.5?
Quite a lot. Innumerable bugs have been fixed, and standards coverage
has been improved significantly. Warning and error messages have been
improved, and so has compile performance. Gate delays, strength
modeling, and floating point delays have all improved since the 0.5
release. If you had trouble with the 0.5 release, the 0.6 release
probably fixes your problem.
Support for large designs spanning multiple files has been improved
dramatically. The usual preprocessor inclusion method still works, but
The 0.6 release adds command files for keeping source file lists, and
automatic library searches for missing modules. The library mechinisms
are compatible with commercial tools, and commercial module libraries
can be used with Icarus Verilog.
Many compiler limitations related to the size and complexity of large
designs have been relaxed or eliminated. There are no known design
size limitations remaining in the compiler. Icarus Verilog should be
able to handle any design that you have the patience to compile.
Diffstat (limited to 'cad/verilog')
| -rw-r--r-- | cad/verilog/Makefile | 21 | ||||
| -rw-r--r-- | cad/verilog/PLIST | 3 | ||||
| -rw-r--r-- | cad/verilog/distinfo | 6 |
3 files changed, 19 insertions, 11 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index b3736615349..8f50752d746 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,9 +1,9 @@ -# $NetBSD: Makefile,v 1.11 2001/09/27 23:17:47 jlam Exp $ +# $NetBSD: Makefile,v 1.12 2002/02/08 01:48:31 dmcmahill Exp $ # -DISTNAME= verilog-0.5 +DISTNAME= verilog-0.6 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.5/ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.6/ MAINTAINER= dmcmahill@netbsd.org HOMEPAGE= http://icarus.com/eda/verilog/index.html @@ -11,16 +11,23 @@ COMMENT= Verilog simulation and synthesis tool (stable release version) BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf -# # turn this back on when ipal comes along a little further #DEPENDS+= ipal-current>=20001210:../../cad/ipal-current CONFLICTS+= verilog-current-[0-9]* GNU_CONFIGURE= yes -USE_GMAKE= yes -# to find ipal.h: -#CPPFLAGS+= -I${LOCALBASE}/include +USE_GMAKE= yes +# +# for ipal.h +#CPPFLAGS+= -I${LOCALBASE}/include +#CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}" CONFIGURE_ARGS+= --without-ipal +YACC= ${LOCALBASE}/bin/bison + +test: build + cd ${WRKSRC} && \ + ${MAKE_ENV} ${MAKE_PROGRAM} check 2>&1 | \ + tee ${WRKDIR}/tests.log .include "../../mk/bsd.pkg.mk" diff --git a/cad/verilog/PLIST b/cad/verilog/PLIST index 0a55a9f5395..4d99fc6fae9 100644 --- a/cad/verilog/PLIST +++ b/cad/verilog/PLIST @@ -1,4 +1,4 @@ -@comment $NetBSD: PLIST,v 1.1 2001/11/01 00:49:32 zuntum Exp $ +@comment $NetBSD: PLIST,v 1.2 2002/02/08 01:48:32 dmcmahill Exp $ bin/iverilog bin/vvp include/ivl_target.h @@ -14,6 +14,7 @@ include/vvm_thread.h lib/libvpi.a lib/libvpip.a lib/libvvm.a +lib/ivl/fpga.tgt lib/ivl/ivl lib/ivl/iverilog.conf lib/ivl/ivlpp diff --git a/cad/verilog/distinfo b/cad/verilog/distinfo index fe87fc720d2..396094e8e61 100644 --- a/cad/verilog/distinfo +++ b/cad/verilog/distinfo @@ -1,5 +1,5 @@ -$NetBSD: distinfo,v 1.3 2001/08/04 01:20:43 dmcmahill Exp $ +$NetBSD: distinfo,v 1.4 2002/02/08 01:48:32 dmcmahill Exp $ -SHA1 (verilog-0.5.tar.gz) = 5f21696e8a908dbbd613f7f55cfbd32abdb7577e -Size (verilog-0.5.tar.gz) = 643405 bytes +SHA1 (verilog-0.6.tar.gz) = 1b6cc6488414497af225732d6574070271e985cc +Size (verilog-0.6.tar.gz) = 730983 bytes SHA1 (patch-ad) = 3c035d32d011d81520e428e3dd9adae435fc63e7 |