diff options
| author | dmcmahill <dmcmahill@pkgsrc.org> | 2006-10-04 23:52:47 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2006-10-04 23:52:47 +0000 |
| commit | 7170cf5e3e291d1b3ab0eca9b746e26091330693 (patch) | |
| tree | 8daee97238352fd3079593313c1ffaff4db09ede /cad/verilog | |
| parent | cd7e9298b919aae0629af34f1608bc311a71ff6a (diff) | |
| download | pkgsrc-7170cf5e3e291d1b3ab0eca9b746e26091330693.tar.gz | |
update to verilog-0.8.3
** Release Notes for Icarus Verilog 0.8.3
This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.
Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.
Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.
The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.
Diffstat (limited to 'cad/verilog')
| -rw-r--r-- | cad/verilog/Makefile | 4 | ||||
| -rw-r--r-- | cad/verilog/distinfo | 10 | ||||
| -rw-r--r-- | cad/verilog/patches/patch-ad | 19 |
3 files changed, 17 insertions, 16 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index 20790dbf770..b298030760e 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,7 +1,7 @@ -# $NetBSD: Makefile,v 1.29 2006/05/28 17:31:26 rillig Exp $ +# $NetBSD: Makefile,v 1.30 2006/10/04 23:52:47 dmcmahill Exp $ # -DISTNAME= verilog-0.8.2 +DISTNAME= verilog-0.8.3 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.8/ diff --git a/cad/verilog/distinfo b/cad/verilog/distinfo index 780f5944f18..fcee57724e1 100644 --- a/cad/verilog/distinfo +++ b/cad/verilog/distinfo @@ -1,6 +1,6 @@ -$NetBSD: distinfo,v 1.10 2006/05/06 19:13:55 dmcmahill Exp $ +$NetBSD: distinfo,v 1.11 2006/10/04 23:52:47 dmcmahill Exp $ -SHA1 (verilog-0.8.2.tar.gz) = ab6966cf85976160c2f6974b7836336271044f71 -RMD160 (verilog-0.8.2.tar.gz) = 4e233941068d3a38f6036700614a21404e7287d4 -Size (verilog-0.8.2.tar.gz) = 1526676 bytes -SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a +SHA1 (verilog-0.8.3.tar.gz) = c3fd64bcdc51d44bde1fd5e168cdff761057c798 +RMD160 (verilog-0.8.3.tar.gz) = b45c7b9811f99ad833e6bf8e5508a72472b7b8f7 +Size (verilog-0.8.3.tar.gz) = 1568131 bytes +SHA1 (patch-ad) = 41628d48a697499e71471defccb596426a098da7 diff --git a/cad/verilog/patches/patch-ad b/cad/verilog/patches/patch-ad index d449d143ae1..1de31dfa409 100644 --- a/cad/verilog/patches/patch-ad +++ b/cad/verilog/patches/patch-ad @@ -1,22 +1,23 @@ -$NetBSD: patch-ad,v 1.7 2004/10/14 22:29:04 dmcmahill Exp $ +$NetBSD: patch-ad,v 1.8 2006/10/04 23:52:48 dmcmahill Exp $ ---- Makefile.in.orig 2003-06-25 03:48:39.000000000 +0200 -+++ Makefile.in 2003-07-12 19:11:41.000000000 +0200 -@@ -170,7 +170,17 @@ - +--- Makefile.in.orig 2006-10-04 17:08:59.000000000 +0000 ++++ Makefile.in 2006-10-04 22:39:41.000000000 +0000 +@@ -171,6 +171,17 @@ lexor.o: lexor.cc parse.h +-parse.o: parse.cc ++ +# work around buggy compilers when compiling the parser with optimization +# make sure no one sneaks a -O* in on us via one of these variables +# set in the environment +CXX_NOOPT=$(CXX:-O%=) +CPPFLAGS_NOOPT=$(CPPFLAGS:-O%=) +CXXFLAGS_NOOPT=$(CXXFLAGS:-O%=) -+ - parse.o: parse.cc + ++parse.o: parse.cc + @[ -d dep ] || mkdir dep + $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o + mv $*.d dep/$*.d - - parse.cc: $(srcdir)/parse.y ++ + parse.cc parse.h: $(srcdir)/parse.y $(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y |