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author | rillig <rillig> | 2006-05-28 17:31:26 +0000 |
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committer | rillig <rillig> | 2006-05-28 17:31:26 +0000 |
commit | 3a86a28e00f2ddf520a89556b7514953ee1a862e (patch) | |
tree | 0d2936984872c1e21094690f70ab279bca941274 /cad/verilog | |
parent | 170034f3ce6f39ff4644e1e19ef8be0aa0dc6acd (diff) | |
download | pkgsrc-3a86a28e00f2ddf520a89556b7514953ee1a862e.tar.gz |
For building verilog, lex is indeed needed.
Diffstat (limited to 'cad/verilog')
-rw-r--r-- | cad/verilog/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index 9dd24b2d234..20790dbf770 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.28 2006/05/22 19:58:48 joerg Exp $ +# $NetBSD: Makefile,v 1.29 2006/05/28 17:31:26 rillig Exp $ # DISTNAME= verilog-0.8.2 @@ -16,7 +16,7 @@ CONFLICTS+= verilog-current-[0-9]* USE_LANGUAGES= c c++ GNU_CONFIGURE= yes -USE_TOOLS+= gmake bison +USE_TOOLS+= gmake bison lex CONFIGURE_ARGS+= --without-ipal TEST_TARGET= check |