diff options
| author | joerg <joerg> | 2009-03-20 19:23:50 +0000 |
|---|---|---|
| committer | joerg <joerg> | 2009-03-20 19:23:50 +0000 |
| commit | 405c61d80251d8e80401aed2264d4bede218cb22 (patch) | |
| tree | 647e974495c5d41703d41ca2e71c9b6063b9153a /cad/verilog | |
| parent | f0f715d4dd4a290c5c6ae716c774f59caf5aa61c (diff) | |
| download | pkgsrc-405c61d80251d8e80401aed2264d4bede218cb22.tar.gz | |
Simply and speed up buildlink3.mk files and processing.
This changes the buildlink3.mk files to use an include guard for the
recursive include. The use of BUILDLINK_DEPTH, BUILDLINK_DEPENDS,
BUILDLINK_PACKAGES and BUILDLINK_ORDER is handled by a single new
variable BUILDLINK_TREE. Each buildlink3.mk file adds a pair of
enter/exit marker, which can be used to reconstruct the tree and
to determine first level includes. Avoiding := for large variables
(BUILDLINK_ORDER) speeds up parse time as += has linear complexity.
The include guard reduces system time by avoiding reading files over and
over again. For complex packages this reduces both %user and %sys time to
half of the former time.
Diffstat (limited to 'cad/verilog')
| -rw-r--r-- | cad/verilog/buildlink3.mk | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/cad/verilog/buildlink3.mk b/cad/verilog/buildlink3.mk index b867dd46409..52d1cadd260 100644 --- a/cad/verilog/buildlink3.mk +++ b/cad/verilog/buildlink3.mk @@ -1,24 +1,17 @@ -# $NetBSD: buildlink3.mk,v 1.5 2006/07/08 23:10:38 jlam Exp $ +# $NetBSD: buildlink3.mk,v 1.6 2009/03/20 19:24:00 joerg Exp $ -BUILDLINK_DEPTH:= ${BUILDLINK_DEPTH}+ -VERILOG_BUILDLINK3_MK:= ${VERILOG_BUILDLINK3_MK}+ +BUILDLINK_TREE+= verilog -.if !empty(BUILDLINK_DEPTH:M+) -BUILDLINK_DEPENDS+= verilog -.endif +.if !defined(VERILOG_BUILDLINK3_MK) +VERILOG_BUILDLINK3_MK:= -BUILDLINK_PACKAGES:= ${BUILDLINK_PACKAGES:Nverilog} -BUILDLINK_PACKAGES+= verilog -BUILDLINK_ORDER:= ${BUILDLINK_ORDER} ${BUILDLINK_DEPTH}verilog - -.if !empty(VERILOG_BUILDLINK3_MK:M+) BUILDLINK_API_DEPENDS.verilog+= verilog>=0.8.1nb1 BUILDLINK_PKGSRCDIR.verilog?= ../../cad/verilog -.endif # VERILOG_BUILDLINK3_MK .include "../../devel/zlib/buildlink3.mk" .include "../../archivers/bzip2/buildlink3.mk" .include "../../devel/gperf/buildlink3.mk" .include "../../devel/readline/buildlink3.mk" +.endif # VERILOG_BUILDLINK3_MK -BUILDLINK_DEPTH:= ${BUILDLINK_DEPTH:S/+$//} +BUILDLINK_TREE+= -verilog |