update verilog-current to 20010407

changes since last snapshot are (from the authors email)


verilog-20010407
--------------------

Still more progress on the new VVP simulation engine:

As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.

In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.

A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.

Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.

Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.

User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.

Non-blocking assignments now work, too.

All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not
work.

*Whew!*

As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!

verilog-20010331
--------------------
More and more progress on VVP. More and more snapshots.

A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.

Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.

I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.

I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.

At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.

9 files changed, 16 insertions, 84 deletions

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 91062366996..c36363e40f6 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.15 2001/04/11 13:38:41 wennmach Exp $
+# $NetBSD: Makefile,v 1.16 2001/04/14 14:47:29 dmcmahill Exp $
 #
 
-DISTNAME=	verilog-20010324
-PKGNAME=	verilog-current-20010324
+DISTNAME=	verilog-20010407
+PKGNAME=	verilog-current-20010407
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/
 
diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5
index 590e3623a84..3af8abefcb4 100644
--- a/cad/verilog-current/files/md5
+++ b/cad/verilog-current/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.12 2001/03/31 00:00:35 dmcmahill Exp $
+$NetBSD: md5,v 1.13 2001/04/14 14:47:31 dmcmahill Exp $
 
-SHA1 (verilog-20010324.tar.gz) = dd79048cf7582937b64f138064d545ca9f4bbbc2
+SHA1 (verilog-20010407.tar.gz) = 2659fe99a6faa6e838399b1213cad3b044625e93
diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum
index 859fef05cb0..9c5daeee9f7 100644
--- a/cad/verilog-current/files/patch-sum
+++ b/cad/verilog-current/files/patch-sum
@@ -1,9 +1,4 @@
-$NetBSD: patch-sum,v 1.11 2001/03/31 00:00:35 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.12 2001/04/14 14:47:31 dmcmahill Exp $
 
-SHA1 (patch-aa) = a965c134268f33615e3b9914f9a20742fc97ad61
-SHA1 (patch-ab) = 505a8ca954e664f366ec9848e777bad056d57c1c
-SHA1 (patch-ac) = e6ca9502c6c39e2b563db74ee567c54e24c82c96
+SHA1 (patch-aa) = 375c8896af276cb1f66f8bf4ca9ff641181d8bc6
 SHA1 (patch-ad) = ebd01d8ffbc55d8cd98682e07c22d2e30218d285
-SHA1 (patch-ae) = 901609b4ca3ab726ccc7a88fb2eed6a42532a1ad
-SHA1 (patch-af) = dac5f8c21f53329f3b366aa03d14fd07e9a60396
-SHA1 (patch-ag) = bd981f93aff766cf27463f59b68e20cac0d80431
diff --git a/cad/verilog-current/patches/patch-aa b/cad/verilog-current/patches/patch-aa
index 348505d76a5..eb8742d50c8 100644
--- a/cad/verilog-current/patches/patch-aa
+++ b/cad/verilog-current/patches/patch-aa
@@ -1,10 +1,11 @@
-$NetBSD: patch-aa,v 1.6 2001/03/31 00:00:35 dmcmahill Exp $
+$NetBSD: patch-aa,v 1.7 2001/04/14 14:47:31 dmcmahill Exp $
 
---- vvp/vpi_mcd.cc.orig	Wed Mar 21 21:24:05 2001
-+++ vvp/vpi_mcd.cc	Fri Mar 30 09:47:26 2001
-@@ -79,4 +79,5 @@
- 	return NULL;
- }
-+static unsigned int vpi_mcd_open_x(char *name, char *mode);
+--- tgt-null/Makefile.in.orig	Thu Dec 14 21:00:31 2000
++++ tgt-null/Makefile.in	Sat Apr 14 09:35:39 2001
+@@ -48,5 +48,5 @@
+ %.o: %.c
+ 	@[ -d dep ] || mkdir dep
+-	$(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
++	$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
+ 	mv $*.d dep
  
- unsigned int vpi_mcd_open(char *name)
diff --git a/cad/verilog-current/patches/patch-ab b/cad/verilog-current/patches/patch-ab
deleted file mode 100644
index df9735025c1..00000000000
--- a/cad/verilog-current/patches/patch-ab
+++ /dev/null
@@ -1,18 +0,0 @@
-$NetBSD: patch-ab,v 1.3 2001/03/31 00:00:35 dmcmahill Exp $
-
---- vvp/functor.cc.orig	Thu Mar 22 00:28:16 2001
-+++ vvp/functor.cc	Fri Mar 30 09:47:50 2001
-@@ -185,5 +185,5 @@
- 	    functor_t idxp = functor_index(idx);
- 	    vvp_ipoint_t next = idxp->port[ipoint_port(idx)];
--	    printf("    set %lx to %u\n", idx, oval);
-+	    printf("    set %lx to %u\n", (unsigned long) idx, oval);
- 	    functor_set(idx, oval);
- 	    idx = next;
-@@ -195,5 +195,5 @@
-       for (unsigned idx = 1 ;  idx < functor_count ;  idx += 1) {
- 	    functor_t cur = functor_index(idx*4);
--	    fprintf(fd, "%10p: out=%x port={%x %x %x %x}\n", idx*4,
-+	    fprintf(fd, "%10p: out=%x port={%x %x %x %x}\n",(void *) (idx*4),
- 		    cur->out, cur->port[0], cur->port[1],
- 		    cur->port[2], cur->port[3]);
diff --git a/cad/verilog-current/patches/patch-ac b/cad/verilog-current/patches/patch-ac
deleted file mode 100644
index 1168ceac530..00000000000
--- a/cad/verilog-current/patches/patch-ac
+++ /dev/null
@@ -1,11 +0,0 @@
-$NetBSD: patch-ac,v 1.1 2001/03/31 00:00:35 dmcmahill Exp $
-
---- tgt-vvp/vvp_scope.c.orig	Tue Mar 20 20:49:43 2001
-+++ tgt-vvp/vvp_scope.c	Fri Mar 30 09:54:01 2001
-@@ -51,5 +51,5 @@
-       }
- 
--      ivl_scope_children(net, draw_scope, net);
-+      ivl_scope_children(net, (ivl_scope_f *) draw_scope, net);
-       return 0;
- }
diff --git a/cad/verilog-current/patches/patch-ae b/cad/verilog-current/patches/patch-ae
deleted file mode 100644
index d851b23a47a..00000000000
--- a/cad/verilog-current/patches/patch-ae
+++ /dev/null
@@ -1,13 +0,0 @@
-$NetBSD: patch-ae,v 1.3 2001/03/31 00:00:35 dmcmahill Exp $
-
---- vvp/Makefile.in.orig	Thu Mar 22 17:37:36 2001
-+++ vvp/Makefile.in	Fri Mar 30 11:08:42 2001
-@@ -40,6 +40,6 @@
- STRIP = @STRIP@
- 
--CPPFLAGS = @CPPFLAGS@ @DEFS@ -DMODULE_DIR=\"$(libdir)/ivl\"
--CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)/..
-+CPPFLAGS = -I. -I$(srcdir)/.. @CPPFLAGS@ @DEFS@ -DMODULE_DIR=\"$(libdir)/ivl\"
-+CXXFLAGS = @CXXFLAGS@ 
- LDFLAGS = @LDFLAGS@
- 
diff --git a/cad/verilog-current/patches/patch-af b/cad/verilog-current/patches/patch-af
deleted file mode 100644
index 98f343a765f..00000000000
--- a/cad/verilog-current/patches/patch-af
+++ /dev/null
@@ -1,11 +0,0 @@
-$NetBSD: patch-af,v 1.1 2001/03/31 00:00:35 dmcmahill Exp $
-
---- tgt-vvp/Makefile.in.orig	Thu Mar 22 00:06:21 2001
-+++ tgt-vvp/Makefile.in	Fri Mar 30 10:45:46 2001
-@@ -47,5 +47,5 @@
- %.o: %.c
- 	@[ -d dep ] || mkdir dep
--	$(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
-+	$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
- 	mv $*.d dep
- 
diff --git a/cad/verilog-current/patches/patch-ag b/cad/verilog-current/patches/patch-ag
deleted file mode 100644
index 0d90975e7e2..00000000000
--- a/cad/verilog-current/patches/patch-ag
+++ /dev/null
@@ -1,11 +0,0 @@
-$NetBSD: patch-ag,v 1.1 2001/03/31 00:00:36 dmcmahill Exp $
-
---- vpi/Makefile.in.orig	Mon Mar 19 20:43:16 2001
-+++ vpi/Makefile.in	Fri Mar 30 11:06:49 2001
-@@ -51,5 +51,5 @@
- %.o: %.c
- 	@[ -d dep ] || mkdir dep
--	$(CC) -Wall $(CPPFLAGS) $(CFLAGS) -I$(srcdir) -I$(srcdir)/.. -MD -c $< -o $*.o
-+	$(CC) -Wall -I$(srcdir) -I$(srcdir)/.. $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $*.o
- 	mv $*.d dep
-