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authordmcmahill <dmcmahill@pkgsrc.org>2000-03-25 21:09:16 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2000-03-25 21:09:16 +0000
commiteb6957f23250b9cfacd72de9a5e37f9231820825 (patch)
tree9ae2d8a6daeb8a912d1179528bde5f3702a96bf0 /cad
parenta9432e7ef01c73fa5e91b15b5f01f4483f4a0718 (diff)
downloadpkgsrc-eb6957f23250b9cfacd72de9a5e37f9231820825.tar.gz
Update to verilog-current-20000318.
Notable changes since the last pkg are (from the snapshot announcement): Parameters are complete. What this means is that I finally got around to supporting defparam, and while I was at it I rewrote the entire parameter handling and added the parameter support included in 1364-2000. I have rewritten major portions of the VVM backend. The vvm_nexus class has been introduced to the fray, and all the device implementations in the VVM library now use the nexus to drive and receive values. An advantage of this scheme is that the t-vvm backend code (in ivl proper) is simpler, and so is the generated C++ code. I also removed most of the template classes. This proved to be a huge compile-time benefit (though compiling twice as fast really only matters for large programs) and it doesn't seem likely to hurt run-time performance. A few remain, either because they seemed harmless (the N-wide logic gates) or I couldn't yet figure out a good way to replace them (vvm_bitset_t). A side benefit of this is that the vvm library may now be a modeling library that ordinary humans can use to write their models in C++. This may provide the unexpected benefit of heading me towards incremental compilation of designs. So who was it who was beating me over the head asking for that?-) I also fixed a few minor problems with the preprocessor. Those of you who reported problems with `includes and `defines should check this out.
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog-current/Makefile9
-rw-r--r--cad/verilog-current/files/md54
-rw-r--r--cad/verilog-current/files/patch-sum4
-rw-r--r--cad/verilog-current/patches/patch-ad8
-rw-r--r--cad/verilog-current/pkg/PLIST14
5 files changed, 21 insertions, 18 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index b228ae306b9..c5131f53f03 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.1.1.1 2000/03/07 16:09:15 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.2 2000/03/25 21:09:16 dmcmahill Exp $
#
-DISTNAME= verilog-20000219
-PKGNAME= verilog-current-20000219
+DISTNAME= verilog-20000318
+PKGNAME= verilog-current-20000318
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
@@ -10,10 +10,11 @@ MAINTAINER= dmcmahill@netbsd.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html
BUILD_DEPENDS+= bison:../../devel/bison
+BUILD_DEPENDS+= gperf:../../devel/gperf
CONFLICTS+= verilog
-GNU_CONFIGURE= YES
+GNU_CONFIGURE= yes
USE_GMAKE= yes
.include "../../mk/bsd.pkg.mk"
diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5
index d51860f2055..1a92d697005 100644
--- a/cad/verilog-current/files/md5
+++ b/cad/verilog-current/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.1.1.1 2000/03/07 16:09:15 dmcmahill Exp $
+$NetBSD: md5,v 1.2 2000/03/25 21:09:16 dmcmahill Exp $
-MD5 (verilog-20000219.tar.gz) = 843630e022912cecf80e198308cf4624
+MD5 (verilog-20000318.tar.gz) = 8d03f502d46986cc8724341e640dfa3b
diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum
index b748dbed2d9..b5a0eb74787 100644
--- a/cad/verilog-current/files/patch-sum
+++ b/cad/verilog-current/files/patch-sum
@@ -1,4 +1,4 @@
-$NetBSD: patch-sum,v 1.2 2000/03/07 20:36:51 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.3 2000/03/25 21:09:16 dmcmahill Exp $
-MD5 (patch-ad) = 35aae681e397bc9d5be0f6765a8adc96
+MD5 (patch-ad) = 1c410a390d7fd9b9db96b933926b30ee
MD5 (patch-ae) = 44921f529c17458cd3ba34d35dc0da77
diff --git a/cad/verilog-current/patches/patch-ad b/cad/verilog-current/patches/patch-ad
index 8d97631011f..77c1159fc4b 100644
--- a/cad/verilog-current/patches/patch-ad
+++ b/cad/verilog-current/patches/patch-ad
@@ -1,11 +1,11 @@
-$NetBSD: patch-ad,v 1.2 2000/03/07 20:36:53 dmcmahill Exp $
+$NetBSD: patch-ad,v 1.3 2000/03/25 21:09:16 dmcmahill Exp $
don't use -O2 on parse.cc because of compiler bugs on sparc and pmax
(maybe others).
---- Makefile.in.orig Sat Feb 5 01:40:35 2000
-+++ Makefile.in Tue Mar 7 12:38:25 2000
-@@ -111,4 +111,6 @@
+--- Makefile.in.orig Thu Mar 16 14:03:03 2000
++++ Makefile.in Sat Mar 25 15:10:16 2000
+@@ -112,4 +112,6 @@
parse.o dep/parse.d: parse.cc
+ $(CXX) -MD -c -I. $(CPPFLAGS) $<
diff --git a/cad/verilog-current/pkg/PLIST b/cad/verilog-current/pkg/PLIST
index c40c8e737d4..d9bc50b8243 100644
--- a/cad/verilog-current/pkg/PLIST
+++ b/cad/verilog-current/pkg/PLIST
@@ -1,16 +1,18 @@
-@comment $NetBSD: PLIST,v 1.1.1.1 2000/03/07 16:09:16 dmcmahill Exp $
-bin/verilog
+@comment $NetBSD: PLIST,v 1.2 2000/03/25 21:09:16 dmcmahill Exp $
bin/gverilog
+bin/verilog
+include/vpi_priv.h
include/vpi_user.h
include/vvm.h
-include/vpi_priv.h
+include/vvm_calltf.h
include/vvm_func.h
include/vvm_gates.h
+include/vvm_nexus.h
+include/vvm_signal.h
include/vvm_thread.h
-include/vvm_calltf.h
+lib/libvvm.a
lib/ivl/ivl
-lib/ivl/system.vpi
lib/ivl/ivlpp
-lib/libvvm.a
+lib/ivl/system.vpi
man/man1/verilog.1
@dirrm lib/ivl