Drop trailing whitespace. Ok'ed by wiz.

16 files changed, 61 insertions, 61 deletions

diff --git a/cad/acs/DESCR b/cad/acs/DESCR
index 3706629235a..a02cce8e7bb 100644
--- a/cad/acs/DESCR
+++ b/cad/acs/DESCR
@@ -5,7 +5,7 @@ command driven.  It can also be run in batch mode or as a server.
 The output is produced as it simulates.  Spice compatible models
 for the MOSFET (level 1,2,3,6) and diode are included in this
 release.
- 
+
 Since it is fully interactive, it is possible to make changes and
 re-simulate quickly.  The interactive design makes it well suited
 to the typical iterative design process used it optimizing a circuit
@@ -14,6 +14,6 @@ Spice in batch mode can be quite intimidating.  This version, while
 still officially in beta test, should be stable enough for basic
 undergraduate teaching and courses in MOS design, but not for
 bipolar design.
- 
+
 In batch mode it is mostly Spice compatible, so it is often possible
 to use the same file for both ACS and Spice.
diff --git a/cad/atlc/DESCR b/cad/atlc/DESCR
index 13bbd56c1ee..97ce1de0e18 100644
--- a/cad/atlc/DESCR
+++ b/cad/atlc/DESCR
@@ -1,11 +1,11 @@
 Atlc is a finite difference programme that is used to calculate the
 properties of a two-conductor electrical transmission line of
 arbitrary cross section. It is used whenever there are no analytical
-formula known, yet you still require an answer. It can calculate: 
+formula known, yet you still require an answer. It can calculate:
 
-  The impedance Zo (in Ohms) 
-  The capacitance per unit length (pF/m) 
-  The inductance per unit length (nF/m) 
+  The impedance Zo (in Ohms)
+  The capacitance per unit length (pF/m)
+  The inductance per unit length (nF/m)
   The velocity of propogation v (m/s)
   The velocity factor, v/c, which is dimensionless.
 
diff --git a/cad/boolean/DESCR b/cad/boolean/DESCR
index e2222992303..25d16ee63aa 100644
--- a/cad/boolean/DESCR
+++ b/cad/boolean/DESCR
@@ -1,24 +1,24 @@
-The program is a viewer and editor for: 
+The program is a viewer and editor for:
   -GDSII files, KEY files (own made extended GDSII in ascii format) and
-   DAVID MANN files (flash format for mask plotting) 
+   DAVID MANN files (flash format for mask plotting)
 
-Features: 
+Features:
  -It allows to draw primitives on a chosen layer, and to manipulate them.
  -stack oriented tools allows zooming while drawing new primitives and
-  editing them. This also makes it possible to draw extremely accurate. 
+  editing them. This also makes it possible to draw extremely accurate.
  -primitives on the layers or/can be transparent  colors and fill patterns
-  can be set on a layer basis 
- -drawing order of layers can be changed 
+  can be set on a layer basis
+ -drawing order of layers can be changed
  -a hiearchy of pictures, named structures, can be handled and manipulated
- -saving as a bitmap and other formats. 
- -measuring distances 
- -adding user defined properties to primitives 
+ -saving as a bitmap and other formats.
+ -measuring distances
+ -adding user defined properties to primitives
 
 
- -boolean OR AND EXOR A-B B-A 
- -positive and negative process offset 
- -circle recognition in polygon and polyline data. 
- -move copy delete etc. 
- -transformations (scaling , rotation , moving) 
- -flatten the hiearchy of the drawing 
- -drivers for CNC (laser and milling machinery) 
+ -boolean OR AND EXOR A-B B-A
+ -positive and negative process offset
+ -circle recognition in polygon and polyline data.
+ -move copy delete etc.
+ -transformations (scaling , rotation , moving)
+ -flatten the hiearchy of the drawing
+ -drivers for CNC (laser and milling machinery)
diff --git a/cad/cascade/DESCR b/cad/cascade/DESCR
index c9226f1d7b8..d46460360fa 100644
--- a/cad/cascade/DESCR
+++ b/cad/cascade/DESCR
@@ -9,4 +9,4 @@ produces a report detailing the performance at each stage.
 
 A summary is produced which shows the relative contributions to the
 total system performance of each block.  This allows easy
-identification of what limits system performance. 
+identification of what limits system performance.
diff --git a/cad/dinotrace/DESCR b/cad/dinotrace/DESCR
index 61981bd6775..6eb6a053902 100644
--- a/cad/dinotrace/DESCR
+++ b/cad/dinotrace/DESCR
@@ -1,4 +1,4 @@
 Dinotrace is a tool designed to aid in viewing Verilog Value Change
 Dump (.vcd), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim
 Binary simulation traces.  It is optimized for rapid design debugging using
-X-Windows Mosaic. 
+X-Windows Mosaic.
diff --git a/cad/electric/DESCR b/cad/electric/DESCR
index d9c70d052b2..22823ed258c 100644
--- a/cad/electric/DESCR
+++ b/cad/electric/DESCR
@@ -1,20 +1,20 @@
 Electric is a sophisticated electrical CAD system that can handle
-many forms of circuit design, including: 
+many forms of circuit design, including:
      Custom IC layout (ASICs), Schematic drawing, Hardware description
-     language specifications, Electro-mechanical hybrid layout 
+     language specifications, Electro-mechanical hybrid layout
 
-Electric has these CAD operations: 
-     Design rule checking (3 options), Electrical rule checking, 
-     Simulation and simulation interface (12 options), Generation (3 options), 
+Electric has these CAD operations:
+     Design rule checking (3 options), Electrical rule checking,
+     Simulation and simulation interface (12 options), Generation (3 options),
      Compaction, Compensation, Routing (4 options), VHDL compilation,
-     Silicon compilation, Network consistency checking (LVS), 
-     Logical Effort analysis, Project Management 
+     Silicon compilation, Network consistency checking (LVS),
+     Logical Effort analysis, Project Management
 
-Electric handles these types of design: 
+Electric handles these types of design:
      MOS (6 CMOS variations, 1 nMOS variation), Bipolar and BiCMOS,
-     Schematics and printed circuits, Digital filters, Temporal logic, Artwork 
+     Schematics and printed circuits, Digital filters, Temporal logic, Artwork
 
-Electric handles these file formats: 
+Electric handles these file formats:
      CIF I/O, GDS I/O, EDIF I/O, DXF I/O, SDF Input,
-     SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output, 
-     PostScript, HPGL, and QuickDraw output 
+     SUE Input, VHDL I/O, Verilog Output, EAGLE, PADS, and ECAD Output,
+     PostScript, HPGL, and QuickDraw output
diff --git a/cad/fastcap/DESCR b/cad/fastcap/DESCR
index ed1c395bd9f..d1296144716 100644
--- a/cad/fastcap/DESCR
+++ b/cad/fastcap/DESCR
@@ -1,13 +1,13 @@
 FastCap is a three-dimensional capacitance extraction program.
 
-FastCap computes self and mutual capacitances between ideal 
-conductors of arbitrary shapes, orientations and sizes.  
+FastCap computes self and mutual capacitances between ideal
+conductors of arbitrary shapes, orientations and sizes. 
 The conductors can be embedded in a dielectric region composed
 of any number of constant-permittivity regions of any shape and
 size.
 
 The algorithm used in FastCap is an acceleration of the
-boundary-element technique for solving the integral equation 
+boundary-element technique for solving the integral equation
 associated with the multiple-conductor, multiple-dielectric
 capacitance extraction problem.  The linear system resulting
 from the boundary-element discretization is solved using a
diff --git a/cad/gerbv/DESCR b/cad/gerbv/DESCR
index 5461c9d9e2e..3fe489b580b 100644
--- a/cad/gerbv/DESCR
+++ b/cad/gerbv/DESCR
@@ -2,4 +2,4 @@ Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are
 generated from PCB CAD system and sent to PCB manufacturers as basis
 for the manufacturing process.
 
-Additionally, gerbv can read and display NC drill files.  
+Additionally, gerbv can read and display NC drill files. 
diff --git a/cad/gnucap/DESCR b/cad/gnucap/DESCR
index e8553ce313a..ad5c4952593 100644
--- a/cad/gnucap/DESCR
+++ b/cad/gnucap/DESCR
@@ -6,7 +6,7 @@ command driven.  It can also be run in batch mode or as a server.
 The output is produced as it simulates.  Spice compatible models
 for the MOSFET (level 1-7) and diode are included in this
 release.
- 
+
 Since it is fully interactive, it is possible to make changes and
 re-simulate quickly.  The interactive design makes it well suited
 to the typical iterative design process used it optimizing a circuit
@@ -15,7 +15,7 @@ design.
 Unlike Spice, the engine is designed to do true mixed-mode
 simulation. Most of the code is in place for future support of
 event driven analog simulation, and true multi-rate simulation.
-	 
+	
 If you are tired of Spice and want a second opinion, you want to
 play with the circuit and want a simulator that is interactive,
 you want to study the source code and want something easier to
diff --git a/cad/gschem/DESCR b/cad/gschem/DESCR
index f0b21868daa..159a252ee49 100644
--- a/cad/gschem/DESCR
+++ b/cad/gschem/DESCR
@@ -7,15 +7,15 @@ layout circuits using a computer.  Standard symbols are used to
 represent the various gates and components which are interconnected
 by nets (wires).  Most vector drawing programs can be used for
 schematic capture but they usually lack one (or more) of the
-following characteristics: 
+following characteristics:
 
  * The awareness of the electrical properties of components, nets,
-   and pins. 
+   and pins.
  * Hierarchical design (having components represent some abstracted
    functionality).  The ability to associate attributes with nets and
-   components. 
- * Generate netlists from the schematic. 
+   components.
+ * Generate netlists from the schematic.
 
   These are all critical features (among others which I cannot recall
 right now) which are shared by all schematic capture programs.  The
-schematic capture program which is part of gEDA is called "gschem". 
+schematic capture program which is part of gEDA is called "gschem".
diff --git a/cad/ipal-current/DESCR b/cad/ipal-current/DESCR
index cf16d952999..fd5ed8a80b6 100644
--- a/cad/ipal-current/DESCR
+++ b/cad/ipal-current/DESCR
@@ -19,6 +19,6 @@ it, producing a Verilog program that logically describes the
 design. This use useful for moving old designs to new tools.
 
 Please note that this package is a development snapshot and while it contains
-the latest and greatest features, it may be buggy as well.  When 
+the latest and greatest features, it may be buggy as well.  When
 available there will be a seperate ipal package which will be made of
 the stable releases.
diff --git a/cad/ng-spice/DESCR b/cad/ng-spice/DESCR
index d5e01630fac..d06080505a5 100644
--- a/cad/ng-spice/DESCR
+++ b/cad/ng-spice/DESCR
@@ -1,6 +1,6 @@
-NG-SPICE is the program being developed as the replacement for Berkeley 
+NG-SPICE is the program being developed as the replacement for Berkeley
 SPICE.  Using the Berkeley code as a starting point, the NG-SPICE team
-is working on improving the build system, adding to the models, and 
+is working on improving the build system, adding to the models, and
 improving the analysis capability.
 
 SPICE is a general-purpose circuit simulation program for nonlinear dc,
diff --git a/cad/oregano/DESCR b/cad/oregano/DESCR
index 6819055bbf9..cf2c2497527 100644
--- a/cad/oregano/DESCR
+++ b/cad/oregano/DESCR
@@ -1,6 +1,6 @@
   Oregano is intended to be an application for schematic capture and
 simulation of electrical circuits. The actual simulation is performed
 by Berkeley SPICE. Oregano can still be used without SPICE, for
-schematic capture. 
+schematic capture.
 
-  Oregano is licensed under the terms of the GNU GPL. 
+  Oregano is licensed under the terms of the GNU GPL.
diff --git a/cad/verilog-current/DESCR b/cad/verilog-current/DESCR
index 813cc45415b..3fa0d7f5888 100644
--- a/cad/verilog-current/DESCR
+++ b/cad/verilog-current/DESCR
@@ -1,10 +1,10 @@
-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a 
+Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
 compiler, compiling source code writen in Verilog (IEEE-1364) into some target
 format. For batch simulation, the compiler can generate C++ code that is
 compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.
-   
+  
 The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's
diff --git a/cad/verilog/DESCR b/cad/verilog/DESCR
index fa22179d8b0..a1f488afa95 100644
--- a/cad/verilog/DESCR
+++ b/cad/verilog/DESCR
@@ -1,10 +1,10 @@
-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a 
+Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
 compiler, compiling source code writen in Verilog (IEEE-1364) into some target
 format. For batch simulation, the compiler can generate C++ code that is
 compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.
-   
+  
 The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's
diff --git a/cad/xchiplogo/DESCR b/cad/xchiplogo/DESCR
index bdaec4778ca..938c8638ad9 100644
--- a/cad/xchiplogo/DESCR
+++ b/cad/xchiplogo/DESCR
@@ -1,10 +1,10 @@
-Xchiplogo reads an ascii bitmap file, and converts it into a  
-magic  or cif file. It is a handy program for creating logos 
+Xchiplogo reads an ascii bitmap file, and converts it into a 
+magic  or cif file. It is a handy program for creating logos
 of text or graphics for  putting  on  VLSI  chips.   At  the
-moment  it  accepts  the  B&W dithered format of XV as the 
+moment  it  accepts  the  B&W dithered format of XV as the
 input. It has got quite a few options for resizing and  get-
 ting rid of many design rule errors that can be found in the
 bitmap file. It has  a smoothing, before and after an  error
 correction  step. The error correction step is pretty simple
-,don't expect miracles, but it works quite  fine  and  spe- 
-cially for text gives a reasonable output.  
+,don't expect miracles, but it works quite  fine  and  spe-
+cially for text gives a reasonable output.