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authordmcmahill <dmcmahill@pkgsrc.org>2002-12-08 04:21:43 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2002-12-08 04:21:43 +0000
commit1e48941c590b927a23bd34617a4be993641c2ab8 (patch)
tree88587b039b93e57336b4aa3101214b5da789d3b3 /cad
parentc5b349c2e7f6132d341030d12c7a61b57b252d5a (diff)
downloadpkgsrc-1e48941c590b927a23bd34617a4be993641c2ab8.tar.gz
initial import of covered-current-20021127.
This is a development snapshot. Packages of the released/stable versions will be imported as 'cad/covered' when available. Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is a development snapshot and while it contains the latest and greatest features, it may be buggy as well. There is a seperate package which is made of the stable releases.
Diffstat (limited to 'cad')
-rw-r--r--cad/covered-current/DESCR17
-rw-r--r--cad/covered-current/Makefile26
-rw-r--r--cad/covered-current/PLIST3
-rw-r--r--cad/covered-current/distinfo4
4 files changed, 50 insertions, 0 deletions
diff --git a/cad/covered-current/DESCR b/cad/covered-current/DESCR
new file mode 100644
index 00000000000..8af360d8997
--- /dev/null
+++ b/cad/covered-current/DESCR
@@ -0,0 +1,17 @@
+Covered is a Verilog code coverage analysis tool that can be useful
+for determining how well a diagnostic test suite is covering the
+design under test. Typically in the design verification work flow, a
+design verification engineer will develop a self-checking test suite
+to verify design elements/functions specified by a design's
+specification document. When the test suite contains all of the tests
+required by the design specification, the test writer may be asking
+him/herself, "How much logic in the design is actually being
+exercised?", "Does my test suite cover all of the logic under test?",
+and "Am I done writing tests for the logic?". When the design
+verification gets to this point, it is often useful to get some
+metrics for determining logic coverage. This is where a code coverage
+utility, such as Covered, is very useful.
+
+Please note that this package is a development snapshot and while it
+contains the latest and greatest features, it may be buggy as well.
+There is a seperate package which is made of the stable releases.
diff --git a/cad/covered-current/Makefile b/cad/covered-current/Makefile
new file mode 100644
index 00000000000..6a408cf7cfa
--- /dev/null
+++ b/cad/covered-current/Makefile
@@ -0,0 +1,26 @@
+# $NetBSD: Makefile,v 1.1.1.1 2002/12/08 04:21:43 dmcmahill Exp $
+#
+
+DISTNAME= covered-${SNAPDATE}
+PKGNAME= covered-current-${SNAPDATE}
+CATEGORIES= cad
+MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=covered/}
+
+MAINTAINER= dmcmahill@netbsd.org
+HOMEPAGE= http://covered.sourceforge.net
+COMMENT= Verilog code coverage analyzer
+
+BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
+BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
+DEPENDS+= verilog{,-current}-[0-9]*:../../cad/verilog
+
+SNAPDATE= 20021127
+GNU_CONFIGURE= YES
+USE_GMAKE= YES
+TEST_DIRS= ${WRKSRC}/diags/regress
+TEST_TARGET= #defined
+
+post-patch:
+ ${CHMOD} 755 ${WRKSRC}/missing
+
+.include "../../mk/bsd.pkg.mk"
diff --git a/cad/covered-current/PLIST b/cad/covered-current/PLIST
new file mode 100644
index 00000000000..a47c582434e
--- /dev/null
+++ b/cad/covered-current/PLIST
@@ -0,0 +1,3 @@
+@comment $NetBSD: PLIST,v 1.1.1.1 2002/12/08 04:21:43 dmcmahill Exp $
+bin/covered
+man/man1/covered.1
diff --git a/cad/covered-current/distinfo b/cad/covered-current/distinfo
new file mode 100644
index 00000000000..1c331e5c582
--- /dev/null
+++ b/cad/covered-current/distinfo
@@ -0,0 +1,4 @@
+$NetBSD: distinfo,v 1.1.1.1 2002/12/08 04:21:43 dmcmahill Exp $
+
+SHA1 (covered-20021127.tar.gz) = d80e5b3bce539eea57c7566f84c5f6b88d37c17b
+Size (covered-20021127.tar.gz) = 818998 bytes