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authormef <mef@pkgsrc.org>2014-01-07 09:43:54 +0000
committermef <mef@pkgsrc.org>2014-01-07 09:43:54 +0000
commitc41a7d081088a9e673f1a39dbdb374e2a1386264 (patch)
tree2ca390c3f4e59d7dff685db74e12a44ab379147a /cad
parente2bb6d8829fc40cb1b8d142033824d263742853d (diff)
downloadpkgsrc-c41a7d081088a9e673f1a39dbdb374e2a1386264.tar.gz
(Upstream)
Icarus Verilog 0.9.7 is Available (August 26th, 2013) ----------------------------- The developers are pleased to announce the next stable release in the 0.9 series, version 0.9.7. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions. It is freely available (open source), is supported on most operating systems, and will be available as a precompiled package for many of these systems. Icarus Verilog 0.9.7 is primarily a bug fix release. Therefore, we recommend people using the 0.9.6 or earlier releases upgrade to 0.9.7 as soon as possible. Version 0.9.7 is the recommended version for all new users. More details, including known limitations, deviation from IEEE Std 1364-2005, where to obtain the source code, and links to some of the precompiled packages can be found in the Release Notes located here: <http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9_7> (pkgsrc) 0.9.4 to 0.9.7 update and two patches are added for DESTDIR and 'mkdir: dep: Not a directory' problem.
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog/Makefile51
-rw-r--r--cad/verilog/PLIST4
-rw-r--r--cad/verilog/distinfo14
-rw-r--r--cad/verilog/patches/patch-aa4
-rw-r--r--cad/verilog/patches/patch-ad24
-rw-r--r--cad/verilog/patches/patch-cadpli_Makefile17
-rw-r--r--cad/verilog/patches/patch-vpi_Makefile29
7 files changed, 119 insertions, 24 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index 1e1c8e20df4..4b8290f6d24 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,14 +1,14 @@
-# $NetBSD: Makefile,v 1.36 2013/07/15 02:02:18 ryoon Exp $
+# $NetBSD: Makefile,v 1.37 2014/01/07 09:43:54 mef Exp $
#
-DISTNAME= verilog-0.9.4
-PKGREVISION= 1
+DISTNAME= verilog-0.9.7
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.9/
MAINTAINER= dmcmahill@NetBSD.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html
COMMENT= Verilog simulation and synthesis tool (stable release version)
+LICENSE= gnu-gpl-v2
PKG_INSTALLATION_TYPES= overwrite pkgviews
@@ -18,9 +18,52 @@ USE_LANGUAGES= c c++
GNU_CONFIGURE= yes
USE_TOOLS+= gmake bison lex
-CONFIGURE_ARGS+= --without-ipal
TEST_TARGET= check
+INSTALLATION_DIRS+= share/ivl
+
+SUBST_CLASSES+= destdir
+SUBST_FILES.destdir= tgt-vhdl/Makefile.in \
+ tgt-fpga/Makefile.in \
+ tgt-null/Makefile.in \
+ tgt-pal/Makefile.in \
+ tgt-stub/Makefile.in \
+ tgt-verilog/Makefile.in \
+ tgt-vvp/Makefile.in
+SUBST_MESSAGE.destdir= Fix DESTDIR in various Makefile.in
+SUBST_STAGE.destdir= pre-configure
+SUBST_SED.destdir= '-e s, $$(libdir)/ivl, $$(DESTDIR)$$(libdir)/ivl,g'
+# Leading TAB
+SUBST_SED.destdir+= '-e s, $$(libdir)/ivl, $$(DESTDIR)$$(libdir)/ivl,g'
+# target:
+SUBST_SED.destdir+= '-e s,^$$(libdir)/ivl,$$(DESTDIR)$$(libdir)/ivl,'
+
+SUBST_CLASSES+= vpi-dest
+SUBST_STAGE.vpi-dest= pre-configure
+SUBST_FILES.vpi-dest= vpi/Makefile.in
+SUBST_MESSAGE.vpi-dest= Fix DESTDIR in vpi/Makefile.in (watch target:)
+SUBST_SED.vpi-dest= '-e s, $$(vpidir)/, $$(DESTDIR)$$(vpidir)/,g'
+# Leading TAB
+SUBST_SED.vpi-dest+= '-e s, $$(vpidir)/, $$(DESTDIR)$$(vpidir)/,g'
+SUBST_SED.vpi-dest+= '-e s,^$$(vpidir)/,$$(DESTDIR)$$(vpidir)/,g'
+
+# Some missing files not installed are handled by SUBST (above)
+# and rest of them are by following target.
+post-install:
+ (cd ${WRKSRC}; ${INSTALL_DATA} \
+ QUICK_START.txt \
+ README.txt \
+ ${DESTDIR}${PREFIX}/share/ivl )
+# include/iverilog
+ (cd ${WRKSRC}; ${INSTALL_DATA} \
+ acc_user.h ivl_target.h veriuser.h vpi_user.h \
+ ${DESTDIR}${PREFIX}/include/iverilog )
+# lib/ivl/include
+ (cd ${WRKSRC}; ${INSTALL_DATA} \
+ constants.vams \
+ disciplines.vams \
+ ${DESTDIR}${PREFIX}/lib/ivl/include )
+
.include "../../devel/zlib/buildlink3.mk"
.include "../../archivers/bzip2/buildlink3.mk"
.include "../../devel/gperf/buildlink3.mk"
diff --git a/cad/verilog/PLIST b/cad/verilog/PLIST
index 1438b27266a..292f0b5b7b8 100644
--- a/cad/verilog/PLIST
+++ b/cad/verilog/PLIST
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.9 2011/04/13 14:19:29 drochner Exp $
+@comment $NetBSD: PLIST,v 1.10 2014/01/07 09:43:54 mef Exp $
bin/iverilog
bin/iverilog-vpi
bin/vvp
@@ -35,3 +35,5 @@ lib/libvpi.a
man/man1/iverilog-vpi.1
man/man1/iverilog.1
man/man1/vvp.1
+share/ivl/QUICK_START.txt
+share/ivl/README.txt
diff --git a/cad/verilog/distinfo b/cad/verilog/distinfo
index b52f3d4285f..7330b4c7fd7 100644
--- a/cad/verilog/distinfo
+++ b/cad/verilog/distinfo
@@ -1,7 +1,9 @@
-$NetBSD: distinfo,v 1.16 2011/04/13 14:19:29 drochner Exp $
+$NetBSD: distinfo,v 1.17 2014/01/07 09:43:54 mef Exp $
-SHA1 (verilog-0.9.4.tar.gz) = 3c249092400f5947d10cb2b9cf4dbe139d8d6c34
-RMD160 (verilog-0.9.4.tar.gz) = dd4f806d7e3840ef62c056bbee8338b56715e6bc
-Size (verilog-0.9.4.tar.gz) = 1200614 bytes
-SHA1 (patch-aa) = 7cc1c3b36dddc0c9c15220282bbcad9429b1a6bd
-SHA1 (patch-ad) = 32c7e4a0724f0a9a98663dfe3e32766a9aced4e7
+SHA1 (verilog-0.9.7.tar.gz) = 714c2a605779957490cca24e3dc01d096dbc1474
+RMD160 (verilog-0.9.7.tar.gz) = 3bac03ca703465a43c5a0a8175a3d27ee00f49a7
+Size (verilog-0.9.7.tar.gz) = 1238088 bytes
+SHA1 (patch-aa) = cf075110416f6db0892129796cd83b8ae8de55fa
+SHA1 (patch-ad) = bf7d227ed3b321021d8aff54cd008f4b2a1557b9
+SHA1 (patch-cadpli_Makefile) = ed21a5f529ac449c26b831cbd5fde052d9ed5466
+SHA1 (patch-vpi_Makefile) = a2c1c120a02593cf2eb75dc3dd458727d230e82d
diff --git a/cad/verilog/patches/patch-aa b/cad/verilog/patches/patch-aa
index 306d67118a1..bdd0b7e06ec 100644
--- a/cad/verilog/patches/patch-aa
+++ b/cad/verilog/patches/patch-aa
@@ -1,4 +1,6 @@
-$NetBSD: patch-aa,v 1.12 2011/04/13 14:19:29 drochner Exp $
+$NetBSD: patch-aa,v 1.13 2014/01/07 09:43:54 mef Exp $
+
+gcc44 fixes
--- elab_net.cc.orig 2010-09-27 17:42:32.000000000 +0000
+++ elab_net.cc
diff --git a/cad/verilog/patches/patch-ad b/cad/verilog/patches/patch-ad
index abfe216ac8a..0de062a87b6 100644
--- a/cad/verilog/patches/patch-ad
+++ b/cad/verilog/patches/patch-ad
@@ -1,25 +1,25 @@
-$NetBSD: patch-ad,v 1.10 2011/04/13 14:19:29 drochner Exp $
+$NetBSD: patch-ad,v 1.11 2014/01/07 09:43:54 mef Exp $
---- Makefile.in.orig 2010-09-27 17:42:32.000000000 +0000
-+++ Makefile.in
-@@ -218,8 +218,19 @@ main.o: main.cc version_tag.h
+make sure no one sneaks a -O* in on us via one of these variables
+set in the environment
+
+--- Makefile.in.orig 2013-08-20 04:10:31.000000000 +0900
++++ Makefile.in 2013-12-20 11:35:09.000000000 +0900
+@@ -222,6 +222,17 @@
lexor.o: lexor.cc parse.h
--parse.o: parse.cc
-+
-+# work around buggy compilers when compiling the parser with optimization
+# make sure no one sneaks a -O* in on us via one of these variables
+# set in the environment
+CXX_NOOPT=$(CXX:-O%=)
+CPPFLAGS_NOOPT=$(CPPFLAGS:-O%=)
+CXXFLAGS_NOOPT=$(CXXFLAGS:-O%=)
-
++
+parse.o: parse.cc
+ @[ -d dep ] || mkdir dep
+ $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o
+ mv $*.d dep/$*.d
-+
- parse.cc parse.h: $(srcdir)/parse.y
- $(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y
- mv parse.cc.h parse.h 2>/dev/null || mv parse.hh parse.h
++
+ parse.o: parse.cc
+
+ # Build this in two steps to avoid parallel build issues (see pr3462585)
diff --git a/cad/verilog/patches/patch-cadpli_Makefile b/cad/verilog/patches/patch-cadpli_Makefile
new file mode 100644
index 00000000000..90143b65ff9
--- /dev/null
+++ b/cad/verilog/patches/patch-cadpli_Makefile
@@ -0,0 +1,17 @@
+$NetBSD: patch-cadpli_Makefile,v 1.1 2014/01/07 09:43:54 mef Exp $
+
+gcc -std=gnu99 -shared -L/usr/lib -Wl,-R/usr/lib -L/usr/pkg/lib -Wl,-R/usr/pkg/lib -o cadpli.vpl cadpli.o ../libveriuser/libveriuser.o -L../vvp -lvpi
+mkdir: dep: Not a directory
+Makefile:52: recipe for target 'dep' failed
+
+--- cadpli/Makefile.in~ 2013-08-20 04:10:31.000000000 +0900
++++ cadpli/Makefile.in 2013-12-20 22:03:29.000000000 +0900
+@@ -51,7 +51,7 @@ check: all
+ dep:
+ mkdir dep
+
+-%.o: %.c
++%.o: %.c dep
+ $(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
+ mv $*.d dep
+
diff --git a/cad/verilog/patches/patch-vpi_Makefile b/cad/verilog/patches/patch-vpi_Makefile
new file mode 100644
index 00000000000..9db3c765d60
--- /dev/null
+++ b/cad/verilog/patches/patch-vpi_Makefile
@@ -0,0 +1,29 @@
+$NetBSD: patch-vpi_Makefile,v 1.1 2014/01/07 09:43:54 mef Exp $
+
+Fix DESTDIR (before SUBST in Makefile is executed)
+
+--- vpi/Makefile.in~ 2013-08-20 04:10:31.000000000 +0900
++++ vpi/Makefile.in 2013-12-20 21:58:51.000000000 +0900
+@@ -133,19 +133,19 @@ $(vpidir)/system.vpi: ./system.vpi
+ $(INSTALL_PROGRAM) ./system.vpi "$(DESTDIR)$(vpidir)/system.vpi"
+
+ $(vpidir)/system.sft: system.sft
+- $(INSTALL_DATA) $< "$(DESTDIR)$@"
++ $(INSTALL_DATA) $< "$@"
+
+ $(vpidir)/va_math.vpi: ./va_math.vpi
+ $(INSTALL_PROGRAM) ./va_math.vpi "$(DESTDIR)$(vpidir)/va_math.vpi"
+
+ $(vpidir)/va_math.sft: va_math.sft
+- $(INSTALL_DATA) $< "$(DESTDIR)$@"
++ $(INSTALL_DATA) $< "$@"
+
+ $(vpidir)/v2005_math.vpi: ./v2005_math.vpi
+ $(INSTALL_PROGRAM) ./v2005_math.vpi "$(DESTDIR)$(vpidir)/v2005_math.vpi"
+
+ $(vpidir)/v2005_math.sft: v2005_math.sft
+- $(INSTALL_DATA) $< "$(DESTDIR)$@"
++ $(INSTALL_DATA) $< "$@"
+
+ installdirs: $(srcdir)/../mkinstalldirs
+ $(srcdir)/../mkinstalldirs "$(DESTDIR)$(libdir)" "$(DESTDIR)$(vpidir)"