update to 20001021 snapshot of verilog-current

from the authors announcement:
-----------------------------

The loadable target module API is starting to take shape.

That is the major thrust nowadays with Icarus Verilog, after all, so
progress is being made here. The biggest change is in fact a philosophy
change. The target module now needs only a single symbol -- target_design --
to receive the whole design. The target module can from there and using
the API access the entire design randomly. So if you wanted to implement
a graphical browser, you could:-)

I've added support for the l-values of procedural assignments, and also
back pointers to objects that reference ivl_nexus_t objects. This closes
the loop so that there should be no dead-ends in the design.

I've clarified and expanded the descriptions in the ivl_target.h header
file. There should be just about enough documentation to properly used
all the various types. (Have any of you tried to write GIMP plug-ins?
Have you looked at the libgimp header files? Have you seen any comments
there?-( I won't ever sink to that level, I hope.)


I've also imtegrated updates to the Cygwin32 port to support loadable
targets under Cygwin32. After much struggling, Venkat managed to discover
the secret magic needed to get load time symbol binding to work. Hopefully
I didn't break it too bad when I changed the API again. (I think it is
still fine.)

6 files changed, 13 insertions, 22 deletions

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 13efab7a276..558f4066f39 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.7 2000/08/06 15:43:34 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.8 2000/10/27 03:59:47 dmcmahill Exp $
 #
 
-DISTNAME=	verilog-20000805
-PKGNAME=	verilog-current-20000805
+DISTNAME=	verilog-20001021
+PKGNAME=	verilog-current-20001021
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/
 
diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5
index 411703646f2..a95614197c7 100644
--- a/cad/verilog-current/files/md5
+++ b/cad/verilog-current/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.7 2000/08/06 15:43:34 dmcmahill Exp $
+$NetBSD: md5,v 1.8 2000/10/27 03:59:47 dmcmahill Exp $
 
-MD5 (verilog-20000805.tar.gz) = d49f7c6ddc7804463c7356cf48f212a3
+MD5 (verilog-20001021.tar.gz) = 2dba2200e0daf5b8d7e424c8bc2fe7e5
diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum
index f775c7f72b3..cc143f64e05 100644
--- a/cad/verilog-current/files/patch-sum
+++ b/cad/verilog-current/files/patch-sum
@@ -1,4 +1,3 @@
-$NetBSD: patch-sum,v 1.8 2000/08/06 15:43:34 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.9 2000/10/27 03:59:48 dmcmahill Exp $
 
-MD5 (patch-ab) = 8e1ec1875b9f1c8a969205c81598be94
-MD5 (patch-ad) = 9a52d6834b76d13b3550755a33935e1e
+MD5 (patch-ad) = 9aa6b9a02f6737fa7b911738942cf7c9
diff --git a/cad/verilog-current/patches/patch-ab b/cad/verilog-current/patches/patch-ab
deleted file mode 100644
index 37070c0c821..00000000000
--- a/cad/verilog-current/patches/patch-ab
+++ /dev/null
@@ -1,11 +0,0 @@
-$NetBSD: patch-ab,v 1.1 2000/06/12 00:41:10 dmcmahill Exp $
-
---- vpi/Makefile.in.orig	Wed May  3 23:37:59 2000
-+++ vpi/Makefile.in	Sun Jun 11 18:59:57 2000
-@@ -42,5 +42,5 @@
- INSTALL_DATA = @INSTALL_DATA@
- 
--CPPFLAGS = @CPPFLAGS@ @DEFS@ -fpic
-+CPPFLAGS = @CPPFLAGS@ @DEFS@ -fPIC
- CXXFLAGS = @CXXFLAGS@
- LDFLAGS = @LDFLAGS@
diff --git a/cad/verilog-current/patches/patch-ad b/cad/verilog-current/patches/patch-ad
index 5e15e6992a5..2d6907075ea 100644
--- a/cad/verilog-current/patches/patch-ad
+++ b/cad/verilog-current/patches/patch-ad
@@ -1,13 +1,14 @@
-$NetBSD: patch-ad,v 1.6 2000/08/06 15:43:35 dmcmahill Exp $
+$NetBSD: patch-ad,v 1.7 2000/10/27 03:59:48 dmcmahill Exp $
 
 work around a c++ -O2 bug which is present on at least sparc 
 and pmax using egcs-1.1.1 
 
 --- Makefile.in.orig	Fri Jul 14 02:12:56 2000
 +++ Makefile.in	Sat Aug  5 17:43:55 2000
-@@ -116,4 +116,6 @@
+@@ -116,4 +116,7 @@
  
  parse.o dep/parse.d: parse.cc
++	@[ -d dep ] || mkdir dep
 +	$(CXX) -MD -c -I. $(CPPFLAGS)  $<
 +	mv parse.d dep/parse.d
  
diff --git a/cad/verilog-current/pkg/PLIST b/cad/verilog-current/pkg/PLIST
index 867d434599a..a0f4e16e244 100644
--- a/cad/verilog-current/pkg/PLIST
+++ b/cad/verilog-current/pkg/PLIST
@@ -1,5 +1,6 @@
-@comment $NetBSD: PLIST,v 1.4 2000/08/06 15:43:35 dmcmahill Exp $
+@comment $NetBSD: PLIST,v 1.5 2000/10/27 03:59:48 dmcmahill Exp $
 bin/iverilog
+include/ivl_target.h
 include/vpi_priv.h
 include/vpi_user.h
 include/vvm.h
@@ -11,6 +12,7 @@ include/vvm_signal.h
 include/vvm_thread.h
 lib/libvvm.a
 lib/ivl/ivl
+lib/ivl/iverilog.conf
 lib/ivl/ivlpp
 lib/ivl/system.vpi
 man/man1/iverilog.1