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authordmcmahill <dmcmahill@pkgsrc.org>2000-05-11 01:33:49 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2000-05-11 01:33:49 +0000
commitdf73e5f2dec90727e596913775be10e2edfa2434 (patch)
tree5abb6029824bdad9f41f0f4e21c7bdd58b1f9b67 /cad
parent9f9f676ac4c8b4fd64cd467e0cce67341cee3728 (diff)
downloadpkgsrc-df73e5f2dec90727e596913775be10e2edfa2434.tar.gz
update to 20000506 snapshot.
changes from the last packaged snapshot (from the authors announcement): ---------------Icarus Verilog 20000506 Snapshot------------------ A lot of internal reworking has been done on this, so there might be problems with things like symbol binding. But I think this is much better then the last snapshot. I am once again starting to think about a stable release. I'll shoot for the end of May, so if there is anything you want to see in that release, start pestering me. The big job has been a rewrite of the symbol table that holds signals. The previous elaboration and lookup code for signals/memories did not work properly when hierarchical names were used in the context of tasks and functions. Also, the old table kept all the signals is a single lookup table that failed to take advantage of knowledge of the current scope. All that is changed. signals are now elaborated after parameters and before processes, so all hierarchical accesses should work properly now, no matter how contorted. I've also fixed some bugs with function/task parameter passing. I've also added some infrastructure for supporting system functions, and I've added an implementation of the $random system function. This currently uses the native random(3) C library function, but once I get access to the standardized algorithm, I'll implement that. There are also a few fixes to elaboration of ternary operators. They were a bit touchy about result bit widths. A few preprocessor bugs have been fixed, especially related to the `ifdef/`endif tokens. People are all the sudden starting to use the Icarus Verilog preprocessor, so some long-standing bugs have been caught. The iverilog command had a few path problems fixed, and the remaining necessary switches have been added. I really encourage people to start using iverilog in place of verilog. The test suite now uses iverilog to run the compiler, so should you. There is a man page.
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog-current/Makefile6
-rw-r--r--cad/verilog-current/files/md54
-rw-r--r--cad/verilog-current/files/patch-sum6
-rw-r--r--cad/verilog-current/patches/patch-aa16
-rw-r--r--cad/verilog-current/patches/patch-ad9
-rw-r--r--cad/verilog-current/pkg/DESCR4
6 files changed, 21 insertions, 24 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 182db4e55d2..f9d28b3f2e0 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.4 2000/04/30 18:15:17 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.5 2000/05/11 01:33:49 dmcmahill Exp $
#
-DISTNAME= verilog-20000428
-PKGNAME= verilog-current-20000428
+DISTNAME= verilog-20000506
+PKGNAME= verilog-current-20000506
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5
index 07ffa27fb7a..9b23e566952 100644
--- a/cad/verilog-current/files/md5
+++ b/cad/verilog-current/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.4 2000/04/30 18:15:17 dmcmahill Exp $
+$NetBSD: md5,v 1.5 2000/05/11 01:33:50 dmcmahill Exp $
-MD5 (verilog-20000428.tar.gz) = a43a130fe53f77bd8e91b836a8ba3e3d
+MD5 (verilog-20000506.tar.gz) = cd9f4183486c49723919e22f91fba96a
diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum
index eab95908629..d0a84bd5911 100644
--- a/cad/verilog-current/files/patch-sum
+++ b/cad/verilog-current/files/patch-sum
@@ -1,5 +1,5 @@
-$NetBSD: patch-sum,v 1.4 2000/04/30 18:15:18 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.5 2000/05/11 01:33:50 dmcmahill Exp $
-MD5 (patch-aa) = 1eb49a0f38e5077d5cd5a04b3d3d825c
-MD5 (patch-ad) = 5778da75ea461b43c731c4b6c05584d2
+MD5 (patch-aa) = c9bef5617308f64272e1e3e50707cb97
+MD5 (patch-ad) = d875516e4fc53270d66101a60bc1e8e5
MD5 (patch-ae) = 44921f529c17458cd3ba34d35dc0da77
diff --git a/cad/verilog-current/patches/patch-aa b/cad/verilog-current/patches/patch-aa
index 73d3545d731..fb833220047 100644
--- a/cad/verilog-current/patches/patch-aa
+++ b/cad/verilog-current/patches/patch-aa
@@ -1,13 +1,13 @@
-$NetBSD: patch-aa,v 1.1 2000/04/30 18:15:18 dmcmahill Exp $
+$NetBSD: patch-aa,v 1.2 2000/05/11 01:33:51 dmcmahill Exp $
---- iverilog.c.orig Fri Apr 28 21:20:14 2000
-+++ iverilog.c Sat Apr 29 08:38:20 2000
-@@ -125,6 +125,6 @@
+--- iverilog.c.orig Thu May 4 21:07:42 2000
++++ iverilog.c Mon May 8 19:55:01 2000
+@@ -133,6 +133,6 @@
}
-- sprintf(tmp, "g++ -O -rdynamic -fno-exceptions -o %s -I%s "
-- "-L%s %s.cc -lvvm -ldl", opath, base, base, opath);
+- sprintf(tmp, "%s -O -rdynamic -fno-exceptions -o %s -I%s "
+- "-L%s %s.cc -lvvm -ldl", CXX, opath, IVL_INC, IVL_LIB,
+ sprintf(tmp, "%s -O -Wl,--export-dynamic -fno-exceptions -o %s -I%s "
-+ "-L%s %s.cc -lvvm %s", CXX, opath, IVL_INC, IVL_LIB, opath, DLLIB);
++ "-L%s %s.cc -lvvm %s", CXX, opath, IVL_INC, IVL_LIB,
+ opath, DLLIB);
- if (verbose_flag)
diff --git a/cad/verilog-current/patches/patch-ad b/cad/verilog-current/patches/patch-ad
index 80b6e5fe941..38e59f5b260 100644
--- a/cad/verilog-current/patches/patch-ad
+++ b/cad/verilog-current/patches/patch-ad
@@ -1,17 +1,10 @@
-$NetBSD: patch-ad,v 1.4 2000/04/30 18:15:18 dmcmahill Exp $
+$NetBSD: patch-ad,v 1.5 2000/05/11 01:33:51 dmcmahill Exp $
don't use -O2 on parse.cc because of compiler bugs on sparc and pmax
(maybe others).
--- Makefile.in.orig Fri Apr 28 12:50:53 2000
+++ Makefile.in Sat Apr 29 08:39:00 2000
-@@ -104,5 +104,5 @@
-
- iverilog: iverilog.c
-- $(CC) $(CPPFLAGS) -o iverilog -DIVL_ROOT='"@libdir@/ivl"' iverilog.c
-+ $(CC) $(CPPFLAGS) -o iverilog -DCXX='"@CXX@"' -DIVL_ROOT='"@libdir@/ivl"' -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' iverilog.c
-
- %.o dep/%.d: %.cc
@@ -115,4 +115,6 @@
parse.o dep/parse.d: parse.cc
diff --git a/cad/verilog-current/pkg/DESCR b/cad/verilog-current/pkg/DESCR
index fa22179d8b0..813cc45415b 100644
--- a/cad/verilog-current/pkg/DESCR
+++ b/cad/verilog-current/pkg/DESCR
@@ -10,3 +10,7 @@ written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.
+
+Please note that this package is a development snapshot and while it contains
+the latest and greatest features, it may be buggy as well. There is a seperate
+verilog package which is made of the stable releases.