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authordmcmahill <dmcmahill@pkgsrc.org>2004-09-02 01:55:47 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2004-09-02 01:55:47 +0000
commitf50dd47782b7677d7b9f23fe603ca62479d0cf0a (patch)
tree254d32b902aeece335534cc6b0f59150a0da4850 /cad
parent308c98aff93025a5fea63ef73a6f0638dd000fa0 (diff)
downloadpkgsrc-f50dd47782b7677d7b9f23fe603ca62479d0cf0a.tar.gz
update to verilog-current-20040828
changes include: Added support for the `default_nettype directine, including the default net type of "none", which turns off implicit net declarations. Signed /, % and >>> in nets should now work properly. Also, various operators of all sorts applied to constants have been improved. Ranges now work on localparams. Added the system tasks $unsigned, $is_signed, $mti_random and $mti-dist_uniform. See the make README.txt for a description of these system functions. Also, flesh out the standard random number generators to match the sequences generated by other compilers. There is now an "sft" file that describes to the compiler the return value of system functions. This allows user supplied system functions to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in the iverilog man page. Include a sft file for the system functions, and move the system functions over to that mechinism. Fix the behavior of $fgets in tight fitting result buffers. A variety of compilation environment fixes have been added. These involve configure scripts and Makefiles. And of course a variety of other bug fixes, and so on and so forth.
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog-current/Makefile6
-rw-r--r--cad/verilog-current/PLIST3
-rw-r--r--cad/verilog-current/distinfo6
3 files changed, 8 insertions, 7 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 3dccf1ad3f3..508e2107162 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.40 2004/06/07 01:09:50 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.41 2004/09/02 01:55:47 dmcmahill Exp $
#
DISTNAME= verilog-${SNAPDATE}
@@ -16,9 +16,8 @@ CONFLICTS+= verilog-[0-9]*
USE_BUILDLINK3= yes
BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
-BUILD_DEPENDS+= gperf>=2.7.2:../../devel/gperf
-SNAPDATE= 20040606
+SNAPDATE= 20040828
GNU_CONFIGURE= yes
USE_GNU_TOOLS+= lex make
CONFIGURE_ARGS+= --without-ipal
@@ -28,5 +27,6 @@ TEST_TARGET= check
.include "../../devel/zlib/buildlink3.mk"
.include "../../archivers/bzip2/buildlink3.mk"
+.include "../../devel/gperf/buildlink3.mk"
.include "../../devel/readline/buildlink3.mk"
.include "../../mk/bsd.pkg.mk"
diff --git a/cad/verilog-current/PLIST b/cad/verilog-current/PLIST
index f67585c4209..52075cb0820 100644
--- a/cad/verilog-current/PLIST
+++ b/cad/verilog-current/PLIST
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.6 2004/03/02 15:34:07 drochner Exp $
+@comment $NetBSD: PLIST,v 1.7 2004/09/02 01:55:47 dmcmahill Exp $
bin/iverilog
bin/iverilog-vpi
bin/vvp
@@ -18,6 +18,7 @@ lib/ivl/ivlpp
lib/ivl/null-s.conf
lib/ivl/null.conf
lib/ivl/null.tgt
+lib/ivl/system.sft
lib/ivl/system.vpi
lib/ivl/vvp-s.conf
lib/ivl/vvp.conf
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index e7570f80254..6c100866632 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.20 2004/06/07 01:09:50 dmcmahill Exp $
+$NetBSD: distinfo,v 1.21 2004/09/02 01:55:47 dmcmahill Exp $
-SHA1 (verilog-20040606.tar.gz) = f91dc4c6e93eef13fab6dbc80144ed48c633d1eb
-Size (verilog-20040606.tar.gz) = 1361219 bytes
+SHA1 (verilog-20040828.tar.gz) = b6e44dc0556247687d068c913bcd4080edfc0285
+Size (verilog-20040828.tar.gz) = 1368773 bytes
SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a