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| author | ryoon <ryoon@pkgsrc.org> | 2019-07-04 13:07:05 +0000 |
|---|---|---|
| committer | ryoon <ryoon@pkgsrc.org> | 2019-07-04 13:07:05 +0000 |
| commit | ab16b2ede742708cce063f5cc4bb4d8ee69f6dea (patch) | |
| tree | d7a9058312fb3543d426ce43572bba971c6361c5 /cad | |
| parent | d59d8afc2b1179bbca4311a9ea53c479af019f17 (diff) | |
| download | pkgsrc-ab16b2ede742708cce063f5cc4bb4d8ee69f6dea.tar.gz | |
Add package specific description
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/MyHDL-gplcver/DESCR | 2 | ||||
| -rw-r--r-- | cad/MyHDL-iverilog/DESCR | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/cad/MyHDL-gplcver/DESCR b/cad/MyHDL-gplcver/DESCR index fd819237dc9..6353b9ae046 100644 --- a/cad/MyHDL-gplcver/DESCR +++ b/cad/MyHDL-gplcver/DESCR @@ -5,3 +5,5 @@ can be viewed as a "scripting language" counterpart of such languages. However, Python is more accurately described as a very high level language (VHLL). MyHDL users have access to the amazing power and elegance of Python for their modeling work. + +This package is GPL Cver cosimulation support for py-MyHDL. diff --git a/cad/MyHDL-iverilog/DESCR b/cad/MyHDL-iverilog/DESCR index fd819237dc9..a2fcfb6caae 100644 --- a/cad/MyHDL-iverilog/DESCR +++ b/cad/MyHDL-iverilog/DESCR @@ -5,3 +5,5 @@ can be viewed as a "scripting language" counterpart of such languages. However, Python is more accurately described as a very high level language (VHLL). MyHDL users have access to the amazing power and elegance of Python for their modeling work. + +This package is Icarus Verilog cosimulation support for py-MyHDL. |