cad/py-PyRTL: import py37-PyRTL-0.8.7

PyRTL provides a collection of classes for pythonic register-transfer
level design, simulation, tracing, and testing suitable for teaching
and research. Simplicity, usability, clarity, and extensibility
rather than performance or optimization is the overarching goal.

4 files changed, 162 insertions, 0 deletions

diff --git a/cad/py-PyRTL/DESCR b/cad/py-PyRTL/DESCR
new file mode 100644
index 00000000000..a51770787d0
--- /dev/null
+++ b/cad/py-PyRTL/DESCR
@@ -0,0 +1,4 @@
+PyRTL provides a collection of classes for pythonic register-transfer
+level design, simulation, tracing, and testing suitable for teaching
+and research. Simplicity, usability, clarity, and extensibility
+rather than performance or optimization is the overarching goal.
diff --git a/cad/py-PyRTL/Makefile b/cad/py-PyRTL/Makefile
new file mode 100644
index 00000000000..4904e727058
--- /dev/null
+++ b/cad/py-PyRTL/Makefile
@@ -0,0 +1,26 @@
+# $NetBSD: Makefile,v 1.1 2019/10/05 06:19:15 ryoon Exp $
+
+DISTNAME=	PyRTL-0.8.7
+PKGNAME=	${PYPKGPREFIX}-${DISTNAME}
+CATEGORIES=	cad python
+MASTER_SITES=	${MASTER_SITE_GITHUB:=UCSBarchlab/}
+GITHUB_PROJECT=	PyRTL
+GITHUB_TAG=	v${PKGVERSION_NOREV}
+
+MAINTAINER=	ryoon@NetBSD.org
+HOMEPAGE=	https://ucsbarchlab.github.io/PyRTL/
+COMMENT=	Register-transfer-level hardware design and simulation
+LICENSE=	modified-bsd
+
+DEPENDS+=	${PYPKGPREFIX}-six-[0-9]*:../../lang/py-six
+
+# 'make test' fails with 2 arithmetic FAILs.
+TEST_DEPENDS+=	${PYPKGPREFIX}-tox-[0-9]*:../../devel/py-tox
+TEST_DEPENDS+=	${PYPKGPREFIX}-nose-[0-9]*:../../devel/py-nose
+
+USE_LANGUAGES=	c # for test
+
+EGG_NAME=	${DISTNAME:tl}
+
+.include "../../lang/python/egg.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/cad/py-PyRTL/PLIST b/cad/py-PyRTL/PLIST
new file mode 100644
index 00000000000..421eb0915bc
--- /dev/null
+++ b/cad/py-PyRTL/PLIST
@@ -0,0 +1,126 @@
+@comment $NetBSD: PLIST,v 1.1 2019/10/05 06:19:15 ryoon Exp $
+${PYSITELIB}/${EGG_INFODIR}/PKG-INFO
+${PYSITELIB}/${EGG_INFODIR}/SOURCES.txt
+${PYSITELIB}/${EGG_INFODIR}/dependency_links.txt
+${PYSITELIB}/${EGG_INFODIR}/requires.txt
+${PYSITELIB}/${EGG_INFODIR}/top_level.txt
+${PYSITELIB}/pyrtl/__init__.py
+${PYSITELIB}/pyrtl/__init__.pyo
+${PYSITELIB}/pyrtl/__init__.pyc
+${PYSITELIB}/pyrtl/compilesim.pyo
+${PYSITELIB}/pyrtl/compilesim.pyc
+${PYSITELIB}/pyrtl/conditional.pyo
+${PYSITELIB}/pyrtl/conditional.pyc
+${PYSITELIB}/pyrtl/core.pyo
+${PYSITELIB}/pyrtl/core.pyc
+${PYSITELIB}/pyrtl/corecircuits.pyo
+${PYSITELIB}/pyrtl/corecircuits.pyc
+${PYSITELIB}/pyrtl/helperfuncs.pyo
+${PYSITELIB}/pyrtl/helperfuncs.pyc
+${PYSITELIB}/pyrtl/inputoutput.pyo
+${PYSITELIB}/pyrtl/inputoutput.pyc
+${PYSITELIB}/pyrtl/memory.pyo
+${PYSITELIB}/pyrtl/memory.pyc
+${PYSITELIB}/pyrtl/passes.pyo
+${PYSITELIB}/pyrtl/passes.pyc
+${PYSITELIB}/pyrtl/pyrtlexceptions.pyo
+${PYSITELIB}/pyrtl/pyrtlexceptions.pyc
+${PYSITELIB}/pyrtl/simulation.pyo
+${PYSITELIB}/pyrtl/simulation.pyc
+${PYSITELIB}/pyrtl/toFirrtl.pyo
+${PYSITELIB}/pyrtl/toFirrtl.pyc
+${PYSITELIB}/pyrtl/transform.pyo
+${PYSITELIB}/pyrtl/transform.pyc
+${PYSITELIB}/pyrtl/verilog.pyo
+${PYSITELIB}/pyrtl/verilog.pyc
+${PYSITELIB}/pyrtl/wire.pyo
+${PYSITELIB}/pyrtl/wire.pyc
+${PYSITELIB}/pyrtl/analysis/__init__.py
+${PYSITELIB}/pyrtl/analysis/__init__.pyo
+${PYSITELIB}/pyrtl/analysis/__init__.pyc
+${PYSITELIB}/pyrtl/analysis/estimate.pyo
+${PYSITELIB}/pyrtl/analysis/estimate.pyc
+${PYSITELIB}/pyrtl/analysis/estimate.py
+${PYSITELIB}/pyrtl/compilesim.py
+${PYSITELIB}/pyrtl/conditional.py
+${PYSITELIB}/pyrtl/core.py
+${PYSITELIB}/pyrtl/corecircuits.py
+${PYSITELIB}/pyrtl/helperfuncs.py
+${PYSITELIB}/pyrtl/inputoutput.py
+${PYSITELIB}/pyrtl/memory.py
+${PYSITELIB}/pyrtl/passes.py
+${PYSITELIB}/pyrtl/pyrtlexceptions.py
+${PYSITELIB}/pyrtl/rtllib/__init__.py
+${PYSITELIB}/pyrtl/rtllib/__init__.pyo
+${PYSITELIB}/pyrtl/rtllib/__init__.pyc
+${PYSITELIB}/pyrtl/rtllib/adders.pyo
+${PYSITELIB}/pyrtl/rtllib/adders.pyc
+${PYSITELIB}/pyrtl/rtllib/aes.pyo
+${PYSITELIB}/pyrtl/rtllib/aes.pyc
+${PYSITELIB}/pyrtl/rtllib/barrel.pyo
+${PYSITELIB}/pyrtl/rtllib/barrel.pyc
+${PYSITELIB}/pyrtl/rtllib/libutils.pyo
+${PYSITELIB}/pyrtl/rtllib/libutils.pyc
+${PYSITELIB}/pyrtl/rtllib/multipliers.pyo
+${PYSITELIB}/pyrtl/rtllib/multipliers.pyc
+${PYSITELIB}/pyrtl/rtllib/muxes.pyo
+${PYSITELIB}/pyrtl/rtllib/muxes.pyc
+${PYSITELIB}/pyrtl/rtllib/prngs.pyo
+${PYSITELIB}/pyrtl/rtllib/prngs.pyc
+${PYSITELIB}/pyrtl/rtllib/testingutils.pyo
+${PYSITELIB}/pyrtl/rtllib/testingutils.pyc
+${PYSITELIB}/pyrtl/rtllib/adders.py
+${PYSITELIB}/pyrtl/rtllib/aes.py
+${PYSITELIB}/pyrtl/rtllib/barrel.py
+${PYSITELIB}/pyrtl/rtllib/libutils.py
+${PYSITELIB}/pyrtl/rtllib/multipliers.py
+${PYSITELIB}/pyrtl/rtllib/muxes.py
+${PYSITELIB}/pyrtl/rtllib/prngs.py
+${PYSITELIB}/pyrtl/rtllib/testingutils.py
+${PYSITELIB}/pyrtl/simulation.py
+${PYSITELIB}/pyrtl/toFirrtl.py
+${PYSITELIB}/pyrtl/transform.py
+${PYSITELIB}/pyrtl/verilog.py
+${PYSITELIB}/pyrtl/wire.py
+${PYSITELIB}/tests/__init__.py
+${PYSITELIB}/tests/__init__.pyo
+${PYSITELIB}/tests/__init__.pyc
+${PYSITELIB}/tests/test_compilesim.pyo
+${PYSITELIB}/tests/test_compilesim.pyc
+${PYSITELIB}/tests/test_conditional.pyo
+${PYSITELIB}/tests/test_conditional.pyc
+${PYSITELIB}/tests/test_core.pyo
+${PYSITELIB}/tests/test_core.pyc
+${PYSITELIB}/tests/test_estimate.pyo
+${PYSITELIB}/tests/test_estimate.pyc
+${PYSITELIB}/tests/test_examples.pyo
+${PYSITELIB}/tests/test_examples.pyc
+${PYSITELIB}/tests/test_helperfuncs.pyo
+${PYSITELIB}/tests/test_helperfuncs.pyc
+${PYSITELIB}/tests/test_inputoutput.pyo
+${PYSITELIB}/tests/test_inputoutput.pyc
+${PYSITELIB}/tests/test_memblock.pyo
+${PYSITELIB}/tests/test_memblock.pyc
+${PYSITELIB}/tests/test_passes.pyo
+${PYSITELIB}/tests/test_passes.pyc
+${PYSITELIB}/tests/test_signed.pyo
+${PYSITELIB}/tests/test_signed.pyc
+${PYSITELIB}/tests/test_simulation.pyo
+${PYSITELIB}/tests/test_simulation.pyc
+${PYSITELIB}/tests/test_transform.pyo
+${PYSITELIB}/tests/test_transform.pyc
+${PYSITELIB}/tests/test_wire.pyo
+${PYSITELIB}/tests/test_wire.pyc
+${PYSITELIB}/tests/test_compilesim.py
+${PYSITELIB}/tests/test_conditional.py
+${PYSITELIB}/tests/test_core.py
+${PYSITELIB}/tests/test_estimate.py
+${PYSITELIB}/tests/test_examples.py
+${PYSITELIB}/tests/test_helperfuncs.py
+${PYSITELIB}/tests/test_inputoutput.py
+${PYSITELIB}/tests/test_memblock.py
+${PYSITELIB}/tests/test_passes.py
+${PYSITELIB}/tests/test_signed.py
+${PYSITELIB}/tests/test_simulation.py
+${PYSITELIB}/tests/test_transform.py
+${PYSITELIB}/tests/test_wire.py
diff --git a/cad/py-PyRTL/distinfo b/cad/py-PyRTL/distinfo
new file mode 100644
index 00000000000..252735bbda2
--- /dev/null
+++ b/cad/py-PyRTL/distinfo
@@ -0,0 +1,6 @@
+$NetBSD: distinfo,v 1.1 2019/10/05 06:19:15 ryoon Exp $
+
+SHA1 (PyRTL-0.8.7.tar.gz) = 35e5b6707786846136873c3dbbe620a623a937a6
+RMD160 (PyRTL-0.8.7.tar.gz) = 48ad50e85fe7dc60c2da9388de01f5acd275daba
+SHA512 (PyRTL-0.8.7.tar.gz) = a7a19045b38f9e7aacc50a984e3c3858e03920b70472850638f074d6267f14e2758743aae30fda646cc62e1897a1df60d77a769f41716c7fb136fe1e0a608833
+Size (PyRTL-0.8.7.tar.gz) = 415294 bytes