update to 0.4.1

changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes

3 files changed, 73 insertions, 42 deletions

diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile
index 0000cf62f00..8829273af8d 100644
--- a/cad/py-MyHDL/Makefile
+++ b/cad/py-MyHDL/Makefile
@@ -1,10 +1,10 @@
-# $NetBSD: Makefile,v 1.6 2004/07/22 09:16:00 recht Exp $
+# $NetBSD: Makefile,v 1.7 2005/01/05 15:20:10 drochner Exp $
 #
 
-DISTNAME=	myhdl-0.2
-PKGNAME=	${PYPKGPREFIX}-MyHDL-0.2
+DISTNAME=	myhdl-0.4.1
+PKGNAME=	${PYPKGPREFIX}-MyHDL-0.4.1
 CATEGORIES=	cad python
-MASTER_SITES=	http://jandecaluwe.com/Tools/MyHDL/
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
 
 MAINTAINER=	tech-pkg@NetBSD.org
 HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
@@ -12,7 +12,7 @@ COMMENT=	Hardware description in Python
 
 USE_BUILDLINK3=	YES
 PYDISTUTILSPKG=	yes
-PYTHON_VERSIONS_ACCEPTED=	22 22pth 23 23pth
+PYTHON_VERSIONS_ACCEPTED=	23 23pth 24 24pth
 
 .include "../../lang/python/extension.mk"
 .include "../../mk/bsd.pkg.mk"
diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST
index 70a5d83aea6..89d54ecf890 100644
--- a/cad/py-MyHDL/PLIST
+++ b/cad/py-MyHDL/PLIST
@@ -1,41 +1,72 @@
-@comment $NetBSD: PLIST,v 1.2 2003/09/14 16:43:46 recht Exp $
-${PYSITELIB}/myhdl/Cosimulation.py
-${PYSITELIB}/myhdl/Cosimulation.pyc
-${PYSITELIB}/myhdl/Cosimulation.pyo
-${PYSITELIB}/myhdl/Signal.py
-${PYSITELIB}/myhdl/Signal.pyc
-${PYSITELIB}/myhdl/Signal.pyo
-${PYSITELIB}/myhdl/Simulation.py
-${PYSITELIB}/myhdl/Simulation.pyc
-${PYSITELIB}/myhdl/Simulation.pyo
+@comment $NetBSD: PLIST,v 1.3 2005/01/05 15:20:10 drochner Exp $
+${PYSITELIB}/myhdl/_Cosimulation.py
+${PYSITELIB}/myhdl/_Cosimulation.pyc
+${PYSITELIB}/myhdl/_Cosimulation.pyo
+${PYSITELIB}/myhdl/_Signal.py
+${PYSITELIB}/myhdl/_Signal.pyc
+${PYSITELIB}/myhdl/_Signal.pyo
+${PYSITELIB}/myhdl/_Simulation.py
+${PYSITELIB}/myhdl/_Simulation.pyc
+${PYSITELIB}/myhdl/_Simulation.pyo
+${PYSITELIB}/myhdl/_Waiter.py
+${PYSITELIB}/myhdl/_Waiter.pyc
+${PYSITELIB}/myhdl/_Waiter.pyo
 ${PYSITELIB}/myhdl/__init__.py
 ${PYSITELIB}/myhdl/__init__.pyc
 ${PYSITELIB}/myhdl/__init__.pyo
+${PYSITELIB}/myhdl/_always_comb.py
+${PYSITELIB}/myhdl/_always_comb.pyc
+${PYSITELIB}/myhdl/_always_comb.pyo
+${PYSITELIB}/myhdl/_bin.py
+${PYSITELIB}/myhdl/_bin.pyc
+${PYSITELIB}/myhdl/_bin.pyo
+${PYSITELIB}/myhdl/_cell_deref.py
+${PYSITELIB}/myhdl/_cell_deref.pyc
+${PYSITELIB}/myhdl/_cell_deref.pyo
+${PYSITELIB}/myhdl/_concat.py
+${PYSITELIB}/myhdl/_concat.pyc
+${PYSITELIB}/myhdl/_concat.pyo
+${PYSITELIB}/myhdl/_delay.py
+${PYSITELIB}/myhdl/_delay.pyc
+${PYSITELIB}/myhdl/_delay.pyo
+${PYSITELIB}/myhdl/_enum.py
+${PYSITELIB}/myhdl/_enum.pyc
+${PYSITELIB}/myhdl/_enum.pyo
+${PYSITELIB}/myhdl/_extractHierarchy.py
+${PYSITELIB}/myhdl/_extractHierarchy.pyc
+${PYSITELIB}/myhdl/_extractHierarchy.pyo
+${PYSITELIB}/myhdl/_intbv.py
+${PYSITELIB}/myhdl/_intbv.pyc
+${PYSITELIB}/myhdl/_intbv.pyo
+${PYSITELIB}/myhdl/_isGenSeq.py
+${PYSITELIB}/myhdl/_isGenSeq.pyc
+${PYSITELIB}/myhdl/_isGenSeq.pyo
+${PYSITELIB}/myhdl/_join.py
+${PYSITELIB}/myhdl/_join.pyc
+${PYSITELIB}/myhdl/_join.pyo
+${PYSITELIB}/myhdl/_misc.py
+${PYSITELIB}/myhdl/_misc.pyc
+${PYSITELIB}/myhdl/_misc.pyo
 ${PYSITELIB}/myhdl/_simulator.py
 ${PYSITELIB}/myhdl/_simulator.pyc
 ${PYSITELIB}/myhdl/_simulator.pyo
-${PYSITELIB}/myhdl/delay.py
-${PYSITELIB}/myhdl/delay.pyc
-${PYSITELIB}/myhdl/delay.pyo
-${PYSITELIB}/myhdl/intbv.py
-${PYSITELIB}/myhdl/intbv.pyc
-${PYSITELIB}/myhdl/intbv.pyo
-${PYSITELIB}/myhdl/test_Cosimulation.py
-${PYSITELIB}/myhdl/test_Cosimulation.pyc
-${PYSITELIB}/myhdl/test_Cosimulation.pyo
-${PYSITELIB}/myhdl/test_Signal.py
-${PYSITELIB}/myhdl/test_Signal.pyc
-${PYSITELIB}/myhdl/test_Signal.pyo
-${PYSITELIB}/myhdl/test_Simulation.py
-${PYSITELIB}/myhdl/test_Simulation.pyc
-${PYSITELIB}/myhdl/test_Simulation.pyo
-${PYSITELIB}/myhdl/test_all.py
-${PYSITELIB}/myhdl/test_all.pyc
-${PYSITELIB}/myhdl/test_all.pyo
-${PYSITELIB}/myhdl/test_intbv.py
-${PYSITELIB}/myhdl/test_intbv.pyc
-${PYSITELIB}/myhdl/test_intbv.pyo
-${PYSITELIB}/myhdl/util.py
-${PYSITELIB}/myhdl/util.pyc
-${PYSITELIB}/myhdl/util.pyo
+${PYSITELIB}/myhdl/_toVerilog/__init__.py
+${PYSITELIB}/myhdl/_toVerilog/__init__.pyc
+${PYSITELIB}/myhdl/_toVerilog/__init__.pyo
+${PYSITELIB}/myhdl/_toVerilog/_analyze.py
+${PYSITELIB}/myhdl/_toVerilog/_analyze.pyc
+${PYSITELIB}/myhdl/_toVerilog/_analyze.pyo
+${PYSITELIB}/myhdl/_toVerilog/_convert.py
+${PYSITELIB}/myhdl/_toVerilog/_convert.pyc
+${PYSITELIB}/myhdl/_toVerilog/_convert.pyo
+${PYSITELIB}/myhdl/_traceSignals.py
+${PYSITELIB}/myhdl/_traceSignals.pyc
+${PYSITELIB}/myhdl/_traceSignals.pyo
+${PYSITELIB}/myhdl/_unparse.py
+${PYSITELIB}/myhdl/_unparse.pyc
+${PYSITELIB}/myhdl/_unparse.pyo
+${PYSITELIB}/myhdl/_util.py
+${PYSITELIB}/myhdl/_util.pyc
+${PYSITELIB}/myhdl/_util.pyo
+@dirrm ${PYSITELIB}/myhdl/_toVerilog
 @dirrm ${PYSITELIB}/myhdl
diff --git a/cad/py-MyHDL/distinfo b/cad/py-MyHDL/distinfo
index 9fdab523298..0d8df5a8848 100644
--- a/cad/py-MyHDL/distinfo
+++ b/cad/py-MyHDL/distinfo
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.1.1.1 2003/06/05 18:50:54 drochner Exp $
+$NetBSD: distinfo,v 1.2 2005/01/05 15:20:10 drochner Exp $
 
-SHA1 (myhdl-0.2.tar.gz) = e9c09d8cac1478eec4986f7a159e2af506a286a8
-Size (myhdl-0.2.tar.gz) = 358159 bytes
+SHA1 (myhdl-0.4.1.tar.gz) = 84096c83351152b1354a331a0b8c3c1bf4098dde
+Size (myhdl-0.4.1.tar.gz) = 1205572 bytes