diff options
| author | dmcmahill <dmcmahill@pkgsrc.org> | 2002-10-22 02:52:17 +0000 |
|---|---|---|
| committer | dmcmahill <dmcmahill@pkgsrc.org> | 2002-10-22 02:52:17 +0000 |
| commit | 138883600f2018be08647d83c573bdb06d48ba69 (patch) | |
| tree | 1c1ddfff6ccc9ec4c53d9d70ee4b64452d20d19a /cad | |
| parent | 3f5989343f71e4cd106c1c8d04d07b40d414949f (diff) | |
| download | pkgsrc-138883600f2018be08647d83c573bdb06d48ba69.tar.gz | |
update to verilog-current-20021019
Release Notes for Icarus Verilog Snapshot 20021019
The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.
The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.
The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.
The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.
Rearrange some of the configure script tests to assure better
compatibility accross platforms.
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/verilog-current/Makefile | 5 | ||||
| -rw-r--r-- | cad/verilog-current/distinfo | 7 | ||||
| -rw-r--r-- | cad/verilog-current/patches/patch-aa | 24 |
3 files changed, 5 insertions, 31 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index 348daec56e7..7dd4c417fe5 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,9 +1,8 @@ -# $NetBSD: Makefile,v 1.30 2002/10/17 01:38:42 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.31 2002/10/22 02:52:17 dmcmahill Exp $ # DISTNAME= verilog-${SNAPDATE} PKGNAME= verilog-current-${SNAPDATE} -PKGREVISION= 1 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ @@ -18,7 +17,7 @@ BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf CONFLICTS+= verilog-[0-9]* -SNAPDATE= 20020921 +SNAPDATE= 20021019 GNU_CONFIGURE= yes USE_GMAKE= yes # diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo index 93621c30868..34758ae581d 100644 --- a/cad/verilog-current/distinfo +++ b/cad/verilog-current/distinfo @@ -1,6 +1,5 @@ -$NetBSD: distinfo,v 1.14 2002/10/17 01:38:43 dmcmahill Exp $ +$NetBSD: distinfo,v 1.15 2002/10/22 02:52:18 dmcmahill Exp $ -SHA1 (verilog-20020921.tar.gz) = 8bd1461ad676194b37c7ba74d3a714eaacf264c9 -Size (verilog-20020921.tar.gz) = 822496 bytes -SHA1 (patch-aa) = 15a15c8c85739bacbd0a85504596be023e9d97c5 +SHA1 (verilog-20021019.tar.gz) = 9e92190d3f6f081ba07a25f3bab05fb3e39693d8 +Size (verilog-20021019.tar.gz) = 825125 bytes SHA1 (patch-ad) = 610a4b597b056f4e951cb75bdb13a9370efec300 diff --git a/cad/verilog-current/patches/patch-aa b/cad/verilog-current/patches/patch-aa deleted file mode 100644 index bd83951479f..00000000000 --- a/cad/verilog-current/patches/patch-aa +++ /dev/null @@ -1,24 +0,0 @@ -$NetBSD: patch-aa,v 1.10 2002/10/17 01:38:43 dmcmahill Exp $ - ---- iverilog-vpi.sh.orig Wed Sep 18 19:25:18 2002 -+++ iverilog-vpi.sh -@@ -84,8 +84,7 @@ OUT=$OUT".vpi" - compile_errors=0 - - # Compile all the source files into object files --for src --in $CCSRC -+for src in $CCSRC - do - base=`basename $src .c` - obj=$base".o" -@@ -95,8 +94,7 @@ do - OBJ="$OBJ $obj" - done - --for src --in $CXSRC -+for src in $CXSRC - do - base=`basename $src .cc` - obj=$base".o" |