diff options
author | ryoon <ryoon@pkgsrc.org> | 2018-12-16 09:05:12 +0000 |
---|---|---|
committer | ryoon <ryoon@pkgsrc.org> | 2018-12-16 09:05:12 +0000 |
commit | d0635d1bbb4fb3c539fa0afa840447eaafd7df2b (patch) | |
tree | 16c4e009e89f7c224d518ca61eee296727262f1e /cad | |
parent | 9d2619101fcaf536d5a43839346566c13e98a265 (diff) | |
download | pkgsrc-d0635d1bbb4fb3c539fa0afa840447eaafd7df2b.tar.gz |
cad/verilator: import verilator-4.006
Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.
Diffstat (limited to 'cad')
-rw-r--r-- | cad/verilator/DESCR | 8 | ||||
-rw-r--r-- | cad/verilator/Makefile | 30 | ||||
-rw-r--r-- | cad/verilator/PLIST | 76 | ||||
-rw-r--r-- | cad/verilator/distinfo | 7 | ||||
-rw-r--r-- | cad/verilator/patches/patch-Makefile.in | 27 |
5 files changed, 148 insertions, 0 deletions
diff --git a/cad/verilator/DESCR b/cad/verilator/DESCR new file mode 100644 index 00000000000..80a4a1a7aa5 --- /dev/null +++ b/cad/verilator/DESCR @@ -0,0 +1,8 @@ +Verilator is the fastest free Verilog HDL simulator, and outperforms +most commercial simulators. Verilator compiles synthesizable +SystemVerilog (generally not test-bench code), plus some SystemVerilog +and Synthesis assertions into single- or multithreaded C++ or +SystemC code. Verilator is designed for large projects where fast +simulation performance is of primary concern, and is especially +well suited to generate executable models of CPUs for embedded +software design teams. diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile new file mode 100644 index 00000000000..35860a8d244 --- /dev/null +++ b/cad/verilator/Makefile @@ -0,0 +1,30 @@ +# $NetBSD: Makefile,v 1.1 2018/12/16 09:05:12 ryoon Exp $ + +DISTNAME= verilator-4.006 +CATEGORIES= cad +MASTER_SITES= https://www.veripool.org/ftp/ +EXTRACT_SUFX= .tgz + +MAINTAINER= ryoon@NetBSD.org +HOMEPAGE= https://www.veripool.org/wiki/verilator +COMMENT= Verilog HDL simulator +LICENSE= gnu-lgpl-v3 OR artistic-2.0 + +GNU_CONFIGURE= yes +FLEX_REQD= 2.6.4 +USE_TOOLS+= bison flex gmake perl pkg-config +USE_LANGUAGES= c c++ + +REPLACE_PERL+= test_regress/*.pl +REPLACE_PERL+= test_regress/t/*.pl + +CONFIGURE_ENV+= ac_cv_path_YACC=bison + +# for long tests +TEST_DEPENDS+= p5-Unix-Processors-[0-9]*:../../sysutils/p5-Unix-Processors +CONFIGURE_ARGS+= --enable-longtests +TEST_TARGET= test + +PKGCONFIG_OVERRIDE+= verilator.pc.in + +.include "../../mk/bsd.pkg.mk" diff --git a/cad/verilator/PLIST b/cad/verilator/PLIST new file mode 100644 index 00000000000..3dbca33baf7 --- /dev/null +++ b/cad/verilator/PLIST @@ -0,0 +1,76 @@ +@comment $NetBSD: PLIST,v 1.1 2018/12/16 09:05:12 ryoon Exp $ +bin/verilator +bin/verilator_bin +bin/verilator_bin_dbg +bin/verilator_coverage +bin/verilator_coverage_bin_dbg +bin/verilator_gantt +bin/verilator_profcfunc +man/man1/verilator.1 +man/man1/verilator_coverage.1 +man/man1/verilator_gantt.1 +man/man1/verilator_profcfunc.1 +share/pkgconfig/verilator.pc +share/verilator/bin/verilator_includer +share/verilator/examples/hello_world_c/Makefile +share/verilator/examples/hello_world_c/sim_main.cpp +share/verilator/examples/hello_world_c/top.v +share/verilator/examples/hello_world_sc/Makefile +share/verilator/examples/hello_world_sc/sc_main.cpp +share/verilator/examples/hello_world_sc/top.v +share/verilator/examples/tracing_c/Makefile +share/verilator/examples/tracing_c/Makefile_obj +share/verilator/examples/tracing_c/input.vc +share/verilator/examples/tracing_c/sim_main.cpp +share/verilator/examples/tracing_c/sub.v +share/verilator/examples/tracing_c/top.v +share/verilator/examples/tracing_sc/Makefile +share/verilator/examples/tracing_sc/Makefile_obj +share/verilator/examples/tracing_sc/input.vc +share/verilator/examples/tracing_sc/sc_main.cpp +share/verilator/examples/tracing_sc/sub.v +share/verilator/examples/tracing_sc/top.v +share/verilator/include/gtkwave/fastlz.c +share/verilator/include/gtkwave/fastlz.h +share/verilator/include/gtkwave/fst_config.h +share/verilator/include/gtkwave/fstapi.c +share/verilator/include/gtkwave/fstapi.h +share/verilator/include/gtkwave/lxt2_write.cpp +share/verilator/include/gtkwave/lxt2_write.h +share/verilator/include/gtkwave/lz4.c +share/verilator/include/gtkwave/lz4.h +share/verilator/include/gtkwave/wavealloca.h +share/verilator/include/verilated.cpp +share/verilator/include/verilated.h +share/verilator/include/verilated.mk +share/verilator/include/verilated.v +share/verilator/include/verilated_config.h +share/verilator/include/verilated_config.h.in +share/verilator/include/verilated_cov.cpp +share/verilator/include/verilated_cov.h +share/verilator/include/verilated_cov_key.h +share/verilator/include/verilated_dpi.cpp +share/verilator/include/verilated_dpi.h +share/verilator/include/verilated_fst_c.cpp +share/verilator/include/verilated_fst_c.h +share/verilator/include/verilated_heavy.h +share/verilator/include/verilated_imp.h +share/verilator/include/verilated_lxt2_c.cpp +share/verilator/include/verilated_lxt2_c.h +share/verilator/include/verilated_save.cpp +share/verilator/include/verilated_save.h +share/verilator/include/verilated_sc.h +share/verilator/include/verilated_sym_props.h +share/verilator/include/verilated_syms.h +share/verilator/include/verilated_threads.cpp +share/verilator/include/verilated_threads.h +share/verilator/include/verilated_unordered_set_map.h +share/verilator/include/verilated_vcd_c.cpp +share/verilator/include/verilated_vcd_c.h +share/verilator/include/verilated_vcd_sc.cpp +share/verilator/include/verilated_vcd_sc.h +share/verilator/include/verilated_vpi.cpp +share/verilator/include/verilated_vpi.h +share/verilator/include/verilatedos.h +share/verilator/include/vltstd/svdpi.h +share/verilator/include/vltstd/vpi_user.h diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo new file mode 100644 index 00000000000..473c84778a5 --- /dev/null +++ b/cad/verilator/distinfo @@ -0,0 +1,7 @@ +$NetBSD: distinfo,v 1.1 2018/12/16 09:05:12 ryoon Exp $ + +SHA1 (verilator-4.006.tgz) = f731c8c8b4b366d806e6a80a52d0b23a5528a054 +RMD160 (verilator-4.006.tgz) = 541a370ceb99a012837ced786bff104510533101 +SHA512 (verilator-4.006.tgz) = f3383b078c22ad8d487fac08ac44b107b7c77a643ced1c6f6e3d03600b696de1d0dabb921b086bca145f361b011d8a3d529f9317a2ccd6a2ec3755067d1cb3e5 +Size (verilator-4.006.tgz) = 2510084 bytes +SHA1 (patch-Makefile.in) = 3c91715cdfaba04120ada7a328b46e0571767e06 diff --git a/cad/verilator/patches/patch-Makefile.in b/cad/verilator/patches/patch-Makefile.in new file mode 100644 index 00000000000..4b6e693b260 --- /dev/null +++ b/cad/verilator/patches/patch-Makefile.in @@ -0,0 +1,27 @@ +$NetBSD: patch-Makefile.in,v 1.1 2018/12/16 09:05:13 ryoon Exp $ + +* Use BSD install command properly. + +--- Makefile.in.orig 2018-10-27 12:25:41.000000000 +0000 ++++ Makefile.in +@@ -299,15 +299,15 @@ VL_INST_DATA_SRCDIR_FILES = \ + + installbin: + $(MKINSTALLDIRS) $(DESTDIR)$(bindir) +- ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator ) +- ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_coverage $(DESTDIR)$(bindir)/verilator_coverage ) +- ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_gantt $(DESTDIR)$(bindir)/verilator_gantt ) +- ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc ) ++ ( cd ${srcdir}/bin ; ${BSD_INSTALL_SCRIPT} verilator $(DESTDIR)$(bindir)/verilator ) ++ ( cd ${srcdir}/bin ; ${BSD_INSTALL_SCRIPT} verilator_coverage $(DESTDIR)$(bindir)/verilator_coverage ) ++ ( cd ${srcdir}/bin ; ${BSD_INSTALL_SCRIPT} verilator_gantt $(DESTDIR)$(bindir)/verilator_gantt ) ++ ( cd ${srcdir}/bin ; ${BSD_INSTALL_SCRIPT} verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc ) + ( cd bin ; $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin ) + ( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg ) + ( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg ) + $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin +- ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer ) ++ ( cd ${srcdir}/bin ; ${BSD_INSTALL_SCRIPT} verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer ) + + # Man files can either be part of the original kit, or built in current directory + # So important we use $^ so VPATH is searched |