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authordrochner <drochner>2003-08-25 11:21:50 +0000
committerdrochner <drochner>2003-08-25 11:21:50 +0000
commitaedf79cbcf49f01b5aaa8e3c8717eabe729e4d3d (patch)
tree311c13f5c482acf3b942bd5a62625a6267f55ef2 /cad
parentd8cc190c39d5adf03ecf0a6776363a244d79df03 (diff)
downloadpkgsrc-aedf79cbcf49f01b5aaa8e3c8717eabe729e4d3d.tar.gz
update to the 20030815 shapshot
changes are basically bugfixes, and improvements in the FPGA synthesis area
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog-current/Makefile4
-rw-r--r--cad/verilog-current/distinfo6
2 files changed, 5 insertions, 5 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index b00f04c20bc..60d88455ac8 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.34 2003/07/17 21:25:27 grant Exp $
+# $NetBSD: Makefile,v 1.35 2003/08/25 11:21:50 drochner Exp $
#
DISTNAME= verilog-${SNAPDATE}
@@ -17,7 +17,7 @@ BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
CONFLICTS+= verilog-[0-9]*
-SNAPDATE= 20030705
+SNAPDATE= 20030815
USE_BUILDLINK2= yes
GNU_CONFIGURE= yes
USE_GMAKE= yes
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index 5273729016b..85ffe0f5525 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.17 2003/07/14 09:51:48 drochner Exp $
+$NetBSD: distinfo,v 1.18 2003/08/25 11:21:50 drochner Exp $
-SHA1 (verilog-20030705.tar.gz) = 1f6d0284b8efa63441e8b2650d11df434a48f374
-Size (verilog-20030705.tar.gz) = 910118 bytes
+SHA1 (verilog-20030815.tar.gz) = 64ee9ca573882fd2a414fc62ee17302fc0bca26e
+Size (verilog-20030815.tar.gz) = 1246700 bytes
SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a