Removed trailing white-space.

8 files changed, 9 insertions, 9 deletions

diff --git a/cad/fastcap/DESCR b/cad/fastcap/DESCR
index d1296144716..f8b6200ecb6 100644
--- a/cad/fastcap/DESCR
+++ b/cad/fastcap/DESCR
@@ -1,7 +1,7 @@
 FastCap is a three-dimensional capacitance extraction program.
 
 FastCap computes self and mutual capacitances between ideal
-conductors of arbitrary shapes, orientations and sizes. 
+conductors of arbitrary shapes, orientations and sizes.
 The conductors can be embedded in a dielectric region composed
 of any number of constant-permittivity regions of any shape and
 size.
diff --git a/cad/gerbv/DESCR b/cad/gerbv/DESCR
index 3fe489b580b..8493e49e4d3 100644
--- a/cad/gerbv/DESCR
+++ b/cad/gerbv/DESCR
@@ -2,4 +2,4 @@ Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are
 generated from PCB CAD system and sent to PCB manufacturers as basis
 for the manufacturing process.
 
-Additionally, gerbv can read and display NC drill files. 
+Additionally, gerbv can read and display NC drill files.
diff --git a/cad/gnetman/DESCR b/cad/gnetman/DESCR
index 3b3608ec273..b7608c39c1e 100644
--- a/cad/gnetman/DESCR
+++ b/cad/gnetman/DESCR
@@ -10,4 +10,4 @@ The long term goal of gnetman is far greater. Two projects under
 consideration include a schematic generator, and a technology
 mapping back-end for Icarus Verilog. Basically, gnetman is a
 netlist manipulation database well suited for low-level
-manipulation of netlists. 
+manipulation of netlists.
diff --git a/cad/gnucap/DESCR b/cad/gnucap/DESCR
index ad5c4952593..802987f5e71 100644
--- a/cad/gnucap/DESCR
+++ b/cad/gnucap/DESCR
@@ -15,7 +15,7 @@ design.
 Unlike Spice, the engine is designed to do true mixed-mode
 simulation. Most of the code is in place for future support of
 event driven analog simulation, and true multi-rate simulation.
-	
+
 If you are tired of Spice and want a second opinion, you want to
 play with the circuit and want a simulator that is interactive,
 you want to study the source code and want something easier to
diff --git a/cad/tnt-mmtl/DESCR b/cad/tnt-mmtl/DESCR
index 78b26964a84..63ea4b7b3b6 100644
--- a/cad/tnt-mmtl/DESCR
+++ b/cad/tnt-mmtl/DESCR
@@ -1,7 +1,7 @@
 TNT-MMTL, the Multilayer Multiconductor Transmission Line 2-D and 2.5-D
 electromagnetic modeling tool suite, generates transmission parameters
 and SPICE models from descriptions of electronics interconnect
-dimensions and materials properties. 
+dimensions and materials properties.
 
 MMTL programs and supporting libraries and documentation have been
 under development at the Mayo Clinic since the mid-1980s. The programs
diff --git a/cad/verilog-current/DESCR b/cad/verilog-current/DESCR
index be6aa3ca681..5b1676fc19a 100644
--- a/cad/verilog-current/DESCR
+++ b/cad/verilog-current/DESCR
@@ -4,7 +4,7 @@ format. For batch simulation, the compiler can generate C++ code that is
 compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.
-  
+
 The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's
diff --git a/cad/verilog/DESCR b/cad/verilog/DESCR
index a1f488afa95..b59d099759e 100644
--- a/cad/verilog/DESCR
+++ b/cad/verilog/DESCR
@@ -4,7 +4,7 @@ format. For batch simulation, the compiler can generate C++ code that is
 compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.
-  
+
 The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's
diff --git a/cad/xchiplogo/DESCR b/cad/xchiplogo/DESCR
index 938c8638ad9..6e97263bd1e 100644
--- a/cad/xchiplogo/DESCR
+++ b/cad/xchiplogo/DESCR
@@ -1,4 +1,4 @@
-Xchiplogo reads an ascii bitmap file, and converts it into a 
+Xchiplogo reads an ascii bitmap file, and converts it into a
 magic  or cif file. It is a handy program for creating logos
 of text or graphics for  putting  on  VLSI  chips.   At  the
 moment  it  accepts  the  B&W dithered format of XV as the
@@ -7,4 +7,4 @@ ting rid of many design rule errors that can be found in the
 bitmap file. It has  a smoothing, before and after an  error
 correction  step. The error correction step is pretty simple
 ,don't expect miracles, but it works quite  fine  and  spe-
-cially for text gives a reasonable output. 
+cially for text gives a reasonable output.