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authordmcmahill <dmcmahill>2001-01-14 19:01:13 +0000
committerdmcmahill <dmcmahill>2001-01-14 19:01:13 +0000
commitbb86d1597f806884877f7cf4646d3fdde0a217d4 (patch)
treeb560072252cb9816c3c848a764d56ea2419f1849 /cad
parentc3996cf49fdcea060e622e5ff98546dcb867201a (diff)
downloadpkgsrc-bb86d1597f806884877f7cf4646d3fdde0a217d4.tar.gz
update to verilog-current-20010113
bug fixes and signed support (yay!). detailed changes since last packaged snapshot from the authors announcements: Icarus Verilog snapshot 20010113 -------------------------------- We're getting close to release candidates. Maybe another snapshot, then I start with making 0.4 release candidates. So lets get this tested so that I can move forward! This snapshot largely fixes a whole bunch of bugs. I'm working feverishly to catch up to the reported bugs, but they are coming in about as fast as I can resolve them. (Not that I'm complaining, mind you. These PRs are really helping me make it better.) But that means I'm going to just concentrate on getting as many PRs done as I can before the release. The syntax of functions and tasks has been expanded to allow parameters. This is not a common thing to do, but someone puts parameters if functions The syntax of functions and tasks has been expanded to allow parameters. This is not a common thing to do, but someone puts parameters if functions so I had a PR to fix:-) Also I caught a problem with executing functions that take no input parameters. In fact, a bunch of function related bugs were fixed. I lost track of em all. Ports of tasks weren't elaborated properly. I fixed this and a few related problems so most legal l-values should work as task port expressions now. Memories within tasks should also work properly now. Speaking of ports, I now report errors when there is a port direction for module ports that don't exist. In fact, there are a whole bunch of cases where I've added required error messages. The %d format of display strings now displays signed negative values as negative values instead of the unsigned equivalent. This goes along with the other signed arithmetic features from the -2000 standard that are now supported. I fixed up the Makefiles (thanks to a contribution) to support build using the VPATH capabilities of the makefile. You should be able to compile for multiple targets now from a shared source directory. Icarus Verilog snapshot 20010106 -------------------------------- I'm just managing to barely keep up with the bug reports arriving in the bug tracking system. I'm pleased with the success of the ivl-bugs robot. These bug reports have allowed me to better manage and record progress. Keep those bug reports coming! I've added support for arrays of integer and time variables, as well as the Verilog 2000 initialization syntax for these types. I have also made some internal changes to integer support. Integers are now just a shorthand for ``reg signed [31:0]'' and signed variable support has made some internal changes to integer support. Integers are now just a shorthand for ``reg signed [31:0]'' and signed variable support has been generalized. This makes it easier on the code generators, as they do not need to know that a variable was a integer, a time, a foo or a bar. I few constant propagation errors have been fixed. Continuous assignments of constants to nets should behave correctly now. Many people noticed lack of expression support for parameters. In fact, the problem was a lack of support for a bunch of specific operators. I've added many operators. This has the side effect of improving constant propagation as well, in some cases finding more dead code to eliminate. This also affected expressions that were index expressions of memories and vector declarations. The / operator in continuous assignment expressions is fixed. There were a few size related issue here that are now fixed. I've added to the i3331364-notes.txt file a clarification of my position on parse of repeat statements. This position is compatible with XL behavior. Passing parameters to user defined functions in behavioral code was pretty darn broken. I managed to fix this. You can tell that not many people use user defined functions:-) (It doesn't help that Icarus Verilog is picky about them.) For vvm, I've put some effort into optimizing the compile time of programs by reducing the size of the output code. I've reduced redundancies some, and used loops to handle vectors where possible. A few bugs related to $dumpvars were cleaned up. Function scopes work.
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog-current/Makefile6
-rw-r--r--cad/verilog-current/files/md54
2 files changed, 5 insertions, 5 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 448d2f91ae7..ce5450bdbdd 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.10 2000/12/19 18:53:51 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.11 2001/01/14 19:01:13 dmcmahill Exp $
#
-DISTNAME= verilog-20001216
-PKGNAME= verilog-current-20001216
+DISTNAME= verilog-20010113
+PKGNAME= verilog-current-20010113
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5
index 98e966ae82a..a53eb6d2008 100644
--- a/cad/verilog-current/files/md5
+++ b/cad/verilog-current/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.10 2000/12/19 18:53:52 dmcmahill Exp $
+$NetBSD: md5,v 1.11 2001/01/14 19:01:14 dmcmahill Exp $
-MD5 (verilog-20001216.tar.gz) = 3d30b951cb9dbb85e8bf74191c7c9abf
+MD5 (verilog-20010113.tar.gz) = 4d871a15c6422a1de562354175128285