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authordmcmahill <dmcmahill>2001-12-15 18:43:37 +0000
committerdmcmahill <dmcmahill>2001-12-15 18:43:37 +0000
commit38ff8cd8ab867cfe52ea1ec127f75f916623c2d2 (patch)
treedc600c859d0b6afaf8dfad75f56ba5315ff777de /cad
parent7991443c0326b755cf66ab95d23c67547a39a922 (diff)
downloadpkgsrc-38ff8cd8ab867cfe52ea1ec127f75f916623c2d2.tar.gz
update to verilog-current-20011209 snapshot.
Many changes since the last packaged snapshot. A sampling of these are: Support for hierarchical names has been largely rewritten. The major consequence of this is that escaped names now have much better support. By now, most any combination of escaped and hierarchical name should work properly, for nets, parameters, and anything else. Output delays for primitive gates, including user defined primitivies, should now work properly. Delays on nets still do not work, although the parser now parses them and prints a "sorry" message. Bugs in support for division(/) and modulus (%) have been fixed. Bugs in l-values of synthesized DFF devices have been fixed. These bugs were related to part selects of vectors in l-values. A few XNF code generator bugs and limitations were fixed. And as usual, a variety of miscellaneous bugs have been fixed in this snapshot. The bit size of the results of some unary redunction operators is now properly handled. Also, similar problems with logical functions have been fixed. force/release now works for variables, though not yet for nets. Assign/deassign already work. many other bugfixes
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog-current/Makefile6
-rw-r--r--cad/verilog-current/distinfo6
2 files changed, 6 insertions, 6 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index a8311c0be32..3986a557077 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.22 2001/10/24 12:27:11 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.23 2001/12/15 18:43:37 dmcmahill Exp $
#
-DISTNAME= verilog-20011020
-PKGNAME= verilog-current-20011020
+DISTNAME= verilog-20011209
+PKGNAME= verilog-current-20011209
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index b1dc5aab469..b9886fa02a6 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.6 2001/10/24 12:27:11 dmcmahill Exp $
+$NetBSD: distinfo,v 1.7 2001/12/15 18:43:37 dmcmahill Exp $
-SHA1 (verilog-20011020.tar.gz) = 34588003e98fb4764ef2168803b3cd4482691c42
-Size (verilog-20011020.tar.gz) = 691955 bytes
+SHA1 (verilog-20011209.tar.gz) = 51e41d85b45c919274df7e107653cf7dbec8fe5a
+Size (verilog-20011209.tar.gz) = 710175 bytes
SHA1 (patch-ad) = 3c035d32d011d81520e428e3dd9adae435fc63e7