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authormef <mef>2014-02-15 13:46:12 +0000
committermef <mef>2014-02-15 13:46:12 +0000
commit877409decebf0c1da4381240605f3aaace0f9a7f (patch)
tree01cf0b3468e02d879c64693ca59efb018157d2b1 /cad
parenta77834518bc216857e2e67907d4cd1ad74beb74f (diff)
downloadpkgsrc-877409decebf0c1da4381240605f3aaace0f9a7f.tar.gz
Update HOMEPAGE.
Diffstat (limited to 'cad')
-rw-r--r--cad/verilog/Makefile4
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index 4b8290f6d24..58e467e9367 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.37 2014/01/07 09:43:54 mef Exp $
+# $NetBSD: Makefile,v 1.38 2014/02/15 13:46:12 mef Exp $
#
DISTNAME= verilog-0.9.7
@@ -6,7 +6,7 @@ CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.9/
MAINTAINER= dmcmahill@NetBSD.org
-HOMEPAGE= http://icarus.com/eda/verilog/index.html
+HOMEPAGE= http://iverilog.icarus.com/
COMMENT= Verilog simulation and synthesis tool (stable release version)
LICENSE= gnu-gpl-v2