diff options
| author | kamil <kamil> | 2016-10-09 13:14:06 +0000 |
|---|---|---|
| committer | kamil <kamil> | 2016-10-09 13:14:06 +0000 |
| commit | 91913d3f52c2d9ada1465d3034458b31f4a8aa24 (patch) | |
| tree | 10a8d4c90f03d3cb38e83aa9d15a2a5fd360a07f /cad | |
| parent | fa6ec2af1e01a04ce093b74bad4849c5db36ded3 (diff) | |
| download | pkgsrc-91913d3f52c2d9ada1465d3034458b31f4a8aa24.tar.gz | |
Import veriwell-2.8.7 as cad/veriwell
VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.
Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/veriwell/DESCR | 5 | ||||
| -rw-r--r-- | cad/veriwell/Makefile | 18 | ||||
| -rw-r--r-- | cad/veriwell/PLIST | 7 | ||||
| -rw-r--r-- | cad/veriwell/distinfo | 6 |
4 files changed, 36 insertions, 0 deletions
diff --git a/cad/veriwell/DESCR b/cad/veriwell/DESCR new file mode 100644 index 00000000000..0bb0f68989b --- /dev/null +++ b/cad/veriwell/DESCR @@ -0,0 +1,5 @@ +VeriWell is a full Verilog simulator. It supports nearly all of the +IEEE1364-1995 standard, as well as PLI 1.0. + +Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in +the mid-1990 and was included with the Thomas and Moorby book. diff --git a/cad/veriwell/Makefile b/cad/veriwell/Makefile new file mode 100644 index 00000000000..05b505ccbba --- /dev/null +++ b/cad/veriwell/Makefile @@ -0,0 +1,18 @@ +# $NetBSD: Makefile,v 1.1 2016/10/09 13:14:06 kamil Exp $ + +DISTNAME= veriwell-2.8.7 +CATEGORIES= cad +MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=veriwell/} + +MAINTAINER= pkgsrc-users@NetBSD.org +HOMEPAGE= https://sourceforge.net/projects/veriwell/ +COMMENT= Verilog Simulator +LICENSE= gnu-gpl-v2 + +GNU_CONFIGURE= yes +USE_LANGUAGES= c c++ + +TEST_TARGET= check + +.include "../../devel/zlib/buildlink3.mk" +.include "../../mk/bsd.pkg.mk" diff --git a/cad/veriwell/PLIST b/cad/veriwell/PLIST new file mode 100644 index 00000000000..b80b73c062e --- /dev/null +++ b/cad/veriwell/PLIST @@ -0,0 +1,7 @@ +@comment $NetBSD: PLIST,v 1.1 2016/10/09 13:14:06 kamil Exp $ +bin/veriwell +include/acc_user.h +include/veriuser.c +include/veriuser.h +lib/libveriwell.la +man/man1/veriwell.1 diff --git a/cad/veriwell/distinfo b/cad/veriwell/distinfo new file mode 100644 index 00000000000..59ab4c5c7c8 --- /dev/null +++ b/cad/veriwell/distinfo @@ -0,0 +1,6 @@ +$NetBSD: distinfo,v 1.1 2016/10/09 13:14:06 kamil Exp $ + +SHA1 (veriwell-2.8.7.tar.gz) = 9ef4e6a25a4fd65db325a89ed89b199547fabbd6 +RMD160 (veriwell-2.8.7.tar.gz) = 3d86c40b353f701d61cab301e0f7c3ec136c88e7 +SHA512 (veriwell-2.8.7.tar.gz) = c0858ce71bd8cfef989e96899bc0d5fc0c919d8248cad0bebde7faf31073cde0423ddb168cf0fabb9f7b46ced7b953ad392627b7e1ad5ea1e7ef75f9524717a8 +Size (veriwell-2.8.7.tar.gz) = 875596 bytes |