diff options
author | mrg <mrg@pkgsrc.org> | 2016-03-29 19:03:07 +0000 |
---|---|---|
committer | mrg <mrg@pkgsrc.org> | 2016-03-29 19:03:07 +0000 |
commit | 1cb2f55fd1aed8e440161e4a87965db11da484dc (patch) | |
tree | 141e7e28f7f19fd940bececc615a8e1939d5641f /emulators/gxemul | |
parent | d714472abcdcdab0fc6c62538c27f8f9165b01b1 (diff) | |
download | pkgsrc-1cb2f55fd1aed8e440161e4a87965db11da484dc.tar.gz |
add support for tgei, tegiu, tlti, tltiu, teqi and tnei instructions.
bump pkg version.
ok @wiz.
Diffstat (limited to 'emulators/gxemul')
-rw-r--r-- | emulators/gxemul/Makefile | 3 | ||||
-rw-r--r-- | emulators/gxemul/distinfo | 4 | ||||
-rw-r--r-- | emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc | 19 | ||||
-rw-r--r-- | emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc | 137 |
4 files changed, 161 insertions, 2 deletions
diff --git a/emulators/gxemul/Makefile b/emulators/gxemul/Makefile index 3cb45514220..7382bad1c5d 100644 --- a/emulators/gxemul/Makefile +++ b/emulators/gxemul/Makefile @@ -1,6 +1,7 @@ -# $NetBSD: Makefile,v 1.52 2014/12/08 20:55:19 ryoon Exp $ +# $NetBSD: Makefile,v 1.53 2016/03/29 19:03:07 mrg Exp $ DISTNAME= gxemul-0.6.0.1 +PKGREVISION= 1 CATEGORIES= emulators MASTER_SITES= http://gxemul.sourceforge.net/src/ diff --git a/emulators/gxemul/distinfo b/emulators/gxemul/distinfo index 0048c3d174a..6c19664a3ae 100644 --- a/emulators/gxemul/distinfo +++ b/emulators/gxemul/distinfo @@ -1,4 +1,4 @@ -$NetBSD: distinfo,v 1.43 2015/11/03 20:30:58 agc Exp $ +$NetBSD: distinfo,v 1.44 2016/03/29 19:03:07 mrg Exp $ SHA1 (gxemul-0.6.0.1.tar.gz) = 8a9b7a6c08628c2a59a6e7e9c7c449c3826b4744 RMD160 (gxemul-0.6.0.1.tar.gz) = 6943173d4149bfe40218715b8ed2c82b5b361e50 @@ -11,6 +11,8 @@ SHA1 (patch-ag) = 09cbf456c27399df985dcc6772b38c54b2a9187d SHA1 (patch-src_components_cpu_CPUDyntransComponent.cc) = 1a70375b3ed409ef43122ce7e6935c07b4ed386d SHA1 (patch-src_components_cpu_M88K__CPUComponent.cc) = 931cdc9a806e9ff48dccb2a63873c52491336b30 SHA1 (patch-src_components_cpu_MIPS__CPUComponent.cc) = 75d8276092fcdc9f548f874e5807ae8e6a2b9eae +SHA1 (patch-src_cpus_cpu_mips.cc) = d239116e4ce5e040a1bdf39b803ca9a05500be53 +SHA1 (patch-src_cpus_cpu_mips_instr.cc) = be40f86a103d2366d13a884d957848d4f680dc61 SHA1 (patch-src_include_components_CPUDyntransComponent.h) = 4fa3c327c4ce5ee9e39e7bc49ce6029b2a7da100 SHA1 (patch-src_include_components_M88K__CPUComponent.h) = afd07ae4df33d0c0a9d3d8c15dca4ef9ee7dd916 SHA1 (patch-src_include_components_MIPS__CPUComponent.h) = 4e49da9af0d220a1ea7c4520d8e7e53d8d84c155 diff --git a/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc b/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc new file mode 100644 index 00000000000..bb4d6718375 --- /dev/null +++ b/emulators/gxemul/patches/patch-src_cpus_cpu_mips.cc @@ -0,0 +1,19 @@ +$NetBSD: patch-src_cpus_cpu_mips.cc,v 1.1 2016/03/29 19:03:07 mrg Exp $ + +implement trap with immediate instructions present in MIPS32. + +--- src/cpus/cpu_mips.cc.orig 2014-08-17 01:45:15.000000000 -0700 ++++ src/cpus/cpu_mips.cc 2016-03-28 11:51:05.000000000 -0700 +@@ -1457,6 +1457,12 @@ + case REGIMM_BLTZALL: + case REGIMM_BGEZAL: + case REGIMM_BGEZALL: ++ case REGIMM_TGEI: ++ case REGIMM_TGEIU: ++ case REGIMM_TLTI: ++ case REGIMM_TLTIU: ++ case REGIMM_TEQI: ++ case REGIMM_TNEI: + debug("%s\t%s,", regimm_names[regimm5], regnames[rs]); + + addr = (dumpaddr + 4) + (imm << 2); diff --git a/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc b/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc new file mode 100644 index 00000000000..3603eec0343 --- /dev/null +++ b/emulators/gxemul/patches/patch-src_cpus_cpu_mips_instr.cc @@ -0,0 +1,137 @@ +$NetBSD: patch-src_cpus_cpu_mips_instr.cc,v 1.1 2016/03/29 19:03:07 mrg Exp $ + +implement trap with immediate instructions present in MIPS32. + +--- src/cpus/cpu_mips_instr.cc.orig 2016-03-28 11:59:41.000000000 -0700 ++++ src/cpus/cpu_mips_instr.cc 2016-03-28 12:04:07.000000000 -0700 +@@ -1461,6 +1461,92 @@ + } + } + ++/* ++ * 1-register + 1-immediate: ++ * ++ * arg[0] = ptr to rs ++ * arg[1] = ([u]int16_t) immediate value ++ */ ++ ++X(tgei) ++{ ++ MODE_int_t a = reg(ic->arg[0]), b = (int16_t)ic->arg[1]; ++ if (a >= b) { ++ /* Synch. PC and cause an exception: */ ++ int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) ++ / sizeof(struct mips_instr_call); ++ cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) ++ << MIPS_INSTR_ALIGNMENT_SHIFT); ++ cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); ++ mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); ++ } ++} ++X(tgeiu) ++{ ++ MODE_uint_t a = reg(ic->arg[0]), b = ic->arg[1]; ++ if (a >= b) { ++ /* Synch. PC and cause an exception: */ ++ int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) ++ / sizeof(struct mips_instr_call); ++ cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) ++ << MIPS_INSTR_ALIGNMENT_SHIFT); ++ cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); ++ mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); ++ } ++} ++X(tlti) ++{ ++ MODE_int_t a = reg(ic->arg[0]), b = (int16_t)ic->arg[1]; ++ if (a < b) { ++ /* Synch. PC and cause an exception: */ ++ int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) ++ / sizeof(struct mips_instr_call); ++ cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) ++ << MIPS_INSTR_ALIGNMENT_SHIFT); ++ cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); ++ mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); ++ } ++} ++X(tltiu) ++{ ++ MODE_uint_t a = reg(ic->arg[0]), b = ic->arg[1]; ++ if (a < b) { ++ /* Synch. PC and cause an exception: */ ++ int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) ++ / sizeof(struct mips_instr_call); ++ cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) ++ << MIPS_INSTR_ALIGNMENT_SHIFT); ++ cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); ++ mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); ++ } ++} ++X(teqi) ++{ ++ MODE_uint_t a = reg(ic->arg[0]), b = (int16_t)ic->arg[1]; ++ if (a == b) { ++ /* Synch. PC and cause an exception: */ ++ int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) ++ / sizeof(struct mips_instr_call); ++ cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) ++ << MIPS_INSTR_ALIGNMENT_SHIFT); ++ cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); ++ mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); ++ } ++} ++X(tnei) ++{ ++ MODE_uint_t a = reg(ic->arg[0]), b = ic->arg[1]; ++ if (a != b) { ++ /* Synch. PC and cause an exception: */ ++ int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) ++ / sizeof(struct mips_instr_call); ++ cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1) ++ << MIPS_INSTR_ALIGNMENT_SHIFT); ++ cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT); ++ mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); ++ } ++} ++ + + /* + * 3-register arithmetic instructions: +@@ -4446,6 +4532,37 @@ + } + break; + ++ case REGIMM_TGEI: ++ case REGIMM_TGEIU: ++ case REGIMM_TLTI: ++ case REGIMM_TLTIU: ++ case REGIMM_TEQI: ++ case REGIMM_TNEI: ++ switch (rt) { ++ case REGIMM_TGEI: ++ ic->f = instr(tgei); ++ break; ++ case REGIMM_TGEIU: ++ ic->f = instr(tgeiu); ++ break; ++ case REGIMM_TLTI: ++ ic->f = instr(tlti); ++ break; ++ case REGIMM_TLTIU: ++ ic->f = instr(tltiu); ++ break; ++ case REGIMM_TEQI: ++ ic->f = instr(teqi); ++ break; ++ case REGIMM_TNEI: ++ ic->f = instr(tnei); ++ break; ++ } ++ ++ ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs]; ++ ic->arg[1] = imm; ++ break; ++ + default:if (!cpu->translation_readahead) + fatal("UNIMPLEMENTED regimm rt=%i\n", rt); + goto bad; |