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author | zuntum <zuntum@pkgsrc.org> | 2001-10-31 22:52:58 +0000 |
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committer | zuntum <zuntum@pkgsrc.org> | 2001-10-31 22:52:58 +0000 |
commit | d038a73ebd432fae3ce355b84443038f88cb7199 (patch) | |
tree | b3c17888184b1b17ed1b1fa28f1697197bb0b4f6 /emulators/swarm/DESCR | |
parent | 70bae73d77e50256a2ee847bd9be11b761bcea01 (diff) | |
download | pkgsrc-d038a73ebd432fae3ce355b84443038f88cb7199.tar.gz |
Move pkg/ files into package's toplevel directory
Diffstat (limited to 'emulators/swarm/DESCR')
-rw-r--r-- | emulators/swarm/DESCR | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/emulators/swarm/DESCR b/emulators/swarm/DESCR new file mode 100644 index 00000000000..21fbb35f752 --- /dev/null +++ b/emulators/swarm/DESCR @@ -0,0 +1,19 @@ +This is SWARM - SoftWare ARM. + +The initial stage in this process is implement a plain software model +of the basic ARM. There are, of course, already software models of +the ARM available, so why do another one? Well, this one will need to +allow the instruction set to be modified at run time, and provide not +just an execution environment, but also a way of monitoring things +like cache hits. + +To this end a hierarchical model of an ARM CPU has been implemented in +C++. It currently supports: + ++ Arm 6 based core. Currently able to handle data processing +instructions, word/byte load and stores, load/store multiple, +branches, 32 bit multiplication, and SWIs. ++ Support for plugging in different caches - be they unified or +separate I & D caches. Currently only a direct mapped cache is +implemented. ++ Compile for SWARM using ARM targeted gcc. |