Restore these changes that were lost in a recent update

When emulating the MIPS DIV and DDIV instructions, check for divide
overflow instead of performing the overflowing divide on the host and
crashing the emulator.  This is needed to run recent versions of the
NetBSD test suite on an emulated MIPS system.

implement trap with immediate instructions present in MIPS32.

3 files changed, 164 insertions, 3 deletions

diff --git a/emulators/gxemul/Makefile b/emulators/gxemul/Makefile
index 3cc25e7f97e..89e1b07e895 100644
--- a/emulators/gxemul/Makefile
+++ b/emulators/gxemul/Makefile
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.65 2019/06/02 09:19:58 gson Exp $
+# $NetBSD: Makefile,v 1.66 2019/06/30 20:33:02 skrll Exp $
 
 DISTNAME=	gxemul-0.6.1
-PKGREVISION=	3
+PKGREVISION=	4
 CATEGORIES=	emulators
 MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=gxemul/}
 
diff --git a/emulators/gxemul/distinfo b/emulators/gxemul/distinfo
index 1c85cf749bf..aad892e63fe 100644
--- a/emulators/gxemul/distinfo
+++ b/emulators/gxemul/distinfo
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.58 2019/06/02 09:19:58 gson Exp $
+$NetBSD: distinfo,v 1.59 2019/06/30 20:33:02 skrll Exp $
 
 SHA1 (gxemul-0.6.1.tar.gz) = 150e495e91a968a49ffc7fe2390c3edff100508d
 RMD160 (gxemul-0.6.1.tar.gz) = 0434bff07970d8828531d222cc8b95c64c2d62f1
@@ -9,6 +9,7 @@ SHA1 (patch-src_components_cpu_CPUDyntransComponent.cc) = dd7a9a83d8abce053e5e61
 SHA1 (patch-src_components_cpu_M88K__CPUComponent.cc) = 4b456721aa0639b91d2dab82fb28f61a951ec8f4
 SHA1 (patch-src_components_cpu_MIPS__CPUComponent.cc) = 9bcb304937ccfa491e37da6f57729854294c420d
 SHA1 (patch-src_console_console.cc) = 0b9c07eaa26a39b20a6f6769cdf02208fc9667d3
+SHA1 (patch-src_cpus_cpu__mips__instr.cc) = 1a39066fad8004b1bf0e9ae6186d943389c4d35f
 SHA1 (patch-src_cpus_cpu_mips.cc) = ad6d9c8b452b1b8422d9194cadfa1c8c3d29ef21
 SHA1 (patch-src_devices_dev__footbridge.cc) = 2dc76e65fff7e6c846d9d06b74bed76075b0c79a
 SHA1 (patch-src_devices_dev__sh4.cc) = 81e3dcc01934c71389a91861343bc8aa32284160
diff --git a/emulators/gxemul/patches/patch-src_cpus_cpu__mips__instr.cc b/emulators/gxemul/patches/patch-src_cpus_cpu__mips__instr.cc
new file mode 100644
index 00000000000..2d013f60193
--- /dev/null
+++ b/emulators/gxemul/patches/patch-src_cpus_cpu__mips__instr.cc
@@ -0,0 +1,160 @@
+$NetBSD: patch-src_cpus_cpu__mips__instr.cc,v 1.1 2019/06/30 20:33:02 skrll Exp $
+
+When emulating the MIPS DIV and DDIV instructions, check for divide
+overflow instead of performing the overflowing divide on the host and
+crashing the emulator.  This is needed to run recent versions of the
+NetBSD test suite on an emulated MIPS system.
+
+implement trap with immediate instructions present in MIPS32.
+
+--- src/cpus/cpu_mips_instr.cc.orig	2019-06-29 16:17:02.938155374 +0000
++++ src/cpus/cpu_mips_instr.cc
+@@ -1275,6 +1275,8 @@ X(divu)
+ 	uint32_t res, rem;
+ 	if (b == 0)
+ 		res = 0, rem = a;
++	else if (a == (int32_t)0x80000000U && b == -1)
++		res = 0, rem = 0;
+ 	else
+ 		res = a / b, rem = a - b*res;
+ 	cpu->cd.mips.lo = (int32_t)res;
+@@ -1300,6 +1302,8 @@ X(ddivu)
+ 	uint64_t res, rem;
+ 	if (b == 0)
+ 		res = 0;
++	else if (a == (int64_t)0x8000000000000000ULL && b == -1)
++		res = 0;
+ 	else
+ 		res = a / b;
+ 	rem = a - b*res;
+@@ -1465,6 +1469,92 @@ X(tne)
+ 	}
+ }
+ 
++/*
++ *  1-register + 1-immediate:
++ *
++ *  arg[0] = ptr to rs
++ *  arg[1] = ([u]int16_t) immediate value
++ */
++
++X(tgei)
++{
++	MODE_int_t a = reg(ic->arg[0]), b = (int16_t)ic->arg[1];
++	if (a >= b) {
++		/*  Synch. PC and cause an exception:  */
++		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
++		    / sizeof(struct mips_instr_call);
++		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
++		    << MIPS_INSTR_ALIGNMENT_SHIFT);
++		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
++		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
++	}
++}
++X(tgeiu)
++{
++	MODE_uint_t a = reg(ic->arg[0]), b = ic->arg[1];
++	if (a >= b) {
++		/*  Synch. PC and cause an exception:  */
++		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
++		    / sizeof(struct mips_instr_call);
++		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
++		    << MIPS_INSTR_ALIGNMENT_SHIFT);
++		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
++		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
++	}
++}
++X(tlti)
++{
++	MODE_int_t a = reg(ic->arg[0]), b = (int16_t)ic->arg[1];
++	if (a < b) {
++		/*  Synch. PC and cause an exception:  */
++		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
++		    / sizeof(struct mips_instr_call);
++		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
++		    << MIPS_INSTR_ALIGNMENT_SHIFT);
++		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
++		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
++	}
++}
++X(tltiu)
++{
++	MODE_uint_t a = reg(ic->arg[0]), b = ic->arg[1];
++	if (a < b) {
++		/*  Synch. PC and cause an exception:  */
++		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
++		    / sizeof(struct mips_instr_call);
++		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
++		    << MIPS_INSTR_ALIGNMENT_SHIFT);
++		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
++		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
++	}
++}
++X(teqi)
++{
++	MODE_uint_t a = reg(ic->arg[0]), b = (int16_t)ic->arg[1];
++	if (a == b) {
++		/*  Synch. PC and cause an exception:  */
++		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
++		    / sizeof(struct mips_instr_call);
++		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
++		    << MIPS_INSTR_ALIGNMENT_SHIFT);
++		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
++		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
++	}
++}
++X(tnei)
++{
++	MODE_uint_t a = reg(ic->arg[0]), b = ic->arg[1];
++	if (a != b) {
++		/*  Synch. PC and cause an exception:  */
++		int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
++		    / sizeof(struct mips_instr_call);
++		cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)
++		    << MIPS_INSTR_ALIGNMENT_SHIFT);
++		cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
++		mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0);
++	}
++}
++
+ 
+ /*
+  *  3-register arithmetic instructions:
+@@ -4478,6 +4568,37 @@ X(to_be_translated)
+ 			}
+ 			break;
+ 
++		case REGIMM_TGEI:
++		case REGIMM_TGEIU:
++		case REGIMM_TLTI:
++		case REGIMM_TLTIU:
++		case REGIMM_TEQI:
++		case REGIMM_TNEI:
++			switch (rt) {
++			case REGIMM_TGEI:
++				ic->f = instr(tgei);
++				break;
++			case REGIMM_TGEIU:
++				ic->f = instr(tgeiu);
++				break;
++			case REGIMM_TLTI:
++				ic->f = instr(tlti);
++				break;
++			case REGIMM_TLTIU:
++				ic->f = instr(tltiu);
++				break;
++			case REGIMM_TEQI:
++				ic->f = instr(teqi);
++				break;
++			case REGIMM_TNEI:
++				ic->f = instr(tnei);
++				break;
++			}
++
++			ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rs];
++			ic->arg[1] = imm;
++			break;
++
+ 		default:if (!cpu->translation_readahead)
+ 				fatal("UNIMPLEMENTED regimm rt=%i\n", rt);
+ 			goto bad;